ASML Holding NV · EURONEXT:ASML
ASML Holding NV — Deutsche Bank Access Asia Conference 2011
32 slides from ASML Holding NV's conference presentation, May 25, 2011
Slide 1: Deutsche Bank Access Asia Conference
Deutsche Bank Access Asia Conference Singapore Craig DeYoung – Vice President Investor Relations May 25, 2011 / Slide 1
Slide 2: Safe Harbor
Safe Harbor "Safe Harbor" Statement under the US Private Securities Litigation Reform Act of 1995: the matters discussed in this document may include forward-looking statements, including statements made about our outlook, realization of backlog, IC unit demand, financial results, average selling pr
Slide 3: ASML's strategy
ASML’s strategy “ To be a technology leader in lithographic systems and software for semiconductor manufacturing, thus enabling our customers to increase the functionality of microchips while reducing the cost and power consumption per function on a chip / Slide 3
Slide 4: ASML: the number 2 semiconductor equipment supplier in the world in 2010
ASML: the number 2 semiconductor equipment supplier in the world in 2010 ASML Headquarters in Veldhoven, the Netherlands / Slide 4
Slide 5: Agenda
Agenda Business Overview Market ASML EUV update Outlook and summary / Slide 5
Slide 6: Business Overview
Business Overview / Slide 6
Slide 7: Net sales
Total net sales M€ 6,000 5,000 4,508 3,768 4,000 3,582 1,521 Q4 Net sales 955 2,954 1,053 Q3 3,000 494 Q2 934 1,176 2,000 958 697 1,596 Q1 930 844 581 1,069 1,000 942 555 1,452 949 919 742 629 277 0 183 2006 2007 2008 2009 2010 2011 Numbers have been rounded for readers’ convenience. / Slide 7
Slide 8: Q1 results - highlights
Q1 results - highlights Net sales of € 1,452 million, 63 systems shipped valued at € 1,284 million, service and field option sales at € 168 million Gross margin of 44.7% Operating margin of 31.0% Net system bookings of 40 systems, € 845 million Backlog at € 3,330 million, 134 systems with ASP of € 2
Slide 9: Key financial trends 2010 – 2011
Key financial trends 2010 – 2011 Consolidated statements of operations M€ Q1 10 Q2 10 Q3 10 Q4 10 Q1 11 Net Sales 742 1,069 1,176 1,521 1,452 Gross profit 298 459 513 685 649 Gross margin % 40.3% 43.0% 43.6% 45.0% 44.7% R&D costs 120 125 137 141 145 SG&A costs 41 42 48 50 54 Income from operations 1
Slide 10: Backlog in value per March 27, 2011
Backlog in value per March 27, 2011 Total value M€ 3,330 New Used Total systems systems systems Technology Units 115 19 134 Value M€ 3,262 68 3,330 ASP M€ 28.4 3.6 24.9 KrF 19% I-Line 2% ArF ArF dry 5% End-use immersion 74% Region (ship to location) Japan 8% Foundry USA IDM 18% Singapore 13% 22% 17%
Slide 11: Market
Market / Slide 11
Slide 12: Business environment
Business environment Semiconductor manufacturers have shown caution in assessing economic impact of Japanese earthquake on their supply chain and end-product markets Although direct impact to the electronics industry world- wide seems limited, it has caused some of our customers to review their exis
Slide 13: 3mma IC revenues/3mma IC inventories
Consumption decreased in March, whereas revenues increased, causing growing IC inventory level 3mma IC revenue, inventory and inventory days 35 3mma IC inventory value (left) Current 3mma inventory value 120 3mma IC revenues (left) at around $27 B 3mma IC revenues/3mma IC inventories [B$] 3mma IC co
Slide 14: DRAM prices and contract prices
DRAM Further recovery of contract prices leads tier 2/3 manufacturers at low 5x nm (closer) to profitability <Customer litho system utilizations high> MAIN DRAM SPOT & CONTRACT PRICES (01/2008 - 2011YTD) 3 1Gb DDR2 800 MHz SPOT PRICE 1Gb DDR2 800 MHz CONTRACT PRICE 2.8 1Gb DDR3 1333 MHz SPOT PRICE A
Slide 15: NAND spot and contract prices
NAND SLC spot prices slide after change in product mix in March, overall chip prices remain quite stable at healthy levels <Customer litho tool utilization remain high> MAIN NAND SPOT & CONTRACT PRICES (01/2008 - 2011YTD) 20 16Gb NAND SLC SPOT PRICE 19 16Gb NAND SLC CONTRACT PRICE 18 32Gb NAND MLC S
Slide 16: ASML EUV update
ASML EUV update / Slide 16
Slide 17: Technology - EUV
Technology - EUV NXE:3100 second generation EUV Three NXE:3100 shipped to date, 3 more to go Progress ongoing to reach target throughput by year end Customer process development started Infrastructure development transitioning to optimization phase (masks, resist, metrology, etc) Revenue recognition
Slide 18: Why EUV? EUV supports IC & Lithography roadmap towards <10nm
Why EUV? EUV supports IC & Lithography roadmap towards <10nm 200 Resolution (half pitch) "Shrink" [nm] KrF 100 80 ArFi ArF AT:1200 60 XT:1400 50 XT:1700i 40 XT:1900i NXT:1950i DPT 30 EUV-ADT LOGIC DPT 20 NXE:3100 NXE:3300 DRAM EUV NXE:3350 QPT 10 DPT NAND 8 02 03 04 05 06 07 08 09 10 11 12 13 14 15
Slide 19: Consumers are the winners
Consumers are the winners Shrink drives manufacturing cost down 10000 $2,305 for 1Gigabyte (GB) 1000 100 $/GByte 10 1 $0.17 for 1 GB 0 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 Note: data iSupply, March 2009. High quality Flash / Slide 19
Slide 20: Shrink drives device complexity which drives litho opportunity
Shrink drives device complexity which drives litho opportunity due to a growing number of critical litho layers Average Logic + DSP + MCU immersion layers Average MPU immersion layers 18 18 16 16 14 14 12 12 10 10 8 8 d A ly.ap e sr sio rn e p EIm xu 6 6 4 4 2 2 0 0 2008 2009 2010 2011 2012 2008 200
Slide 21: Increasing immersion layers per node, per year with shrink in memory too
Increasing immersion layers per node, per year with shrink in memory too Average DRAM immersion layers Average NAND immersion layers 10 10 8 8 6 6 4 4 2 2 0 0 2008 2009 2010 2011 2012 2008 2009 2010 2011 2012 Node 8x, 6x 6x, 5x 5x, 4x 4x, 3x 3x, 2x Node 5x, 4x 4x, 3x 4x, 3x 3x, 2x 2x, 1x Source: ASM
Slide 22: Litho Patterning Process Steps
Typical Patterning Schemes for Critical Layers 2011 Strip & Clean 2013 Hard Mask Etch Defect Inspect Metrology Develop Expose Litho Patterning Process Steps Resist Organic BARC Inorganic BARC Cap Layer Hard Mask Logic NAND DRAM Logic NAND DRAM 32nm 2x nm 3x nm 22nm 1x nm 2xnm ArFi Spacer DPT Spacer
Slide 23: Cost Impact of Double Patterning
Cost Impact of Double Patterning 3.0 Relative Patterning Cost 2.5 Reticle Strip/Clean 2.0 Etch Metrology 1.5 CVD 1.0 Litho chemicals Track 0.5 Litho - Logic NAND DRAM Logic NAND DRAM ALL 32nm 2x nm 3x nm 22nm 1x nm 2xnm - ArFi 1D 1D 2x Litho- Double 2D EUV Spacer Spacer Etch Spacer Spacer Source: AS
Slide 24: Cycle Time Impact of Double Patterning
Cycle Time Impact of Double Patterning 3.5 3.0 Relative Cycle Time 2.5 Strip/Clean 2.0 Etch Metrology 1.5 CVD 1.0 Litho 0.5 - Logic NAND DRAM Logic NAND DRAM ALL 32nm 2x nm 3x nm 22nm 1x nm 2xnm - ArFi 1D 1D 2x Litho- Double 2D EUV Spacer Spacer Etch Spacer Spacer Source: ASML Strategic Marketing /
Slide 25: EUV lowers overall costs for customer, while increasing litho costs
EUV lowers overall costs for customer, while increasing litho costs Costs per layer: Metrology Strip/Clean Spacer etch ArFi Spacer imaging: BARC/ACL/SiON etch Overall patterning costs (including litho, etching, etc.): Patterning steps per device layer Metrology • Strip/Clean Trim Etch 70.82 €/wafer
Slide 26: ASML's Unique Holistic Litho Optimisation & Control
ASML’s Unique Holistic Litho Optimisation & Control of future low k1, DP and EUV litho processes ••Optimize Optimize scanner scanner Source-Mask Optimization Tachyon SMO Pre-reticle illumination illumination conditions conditions ••Enlarge Enlarge process process window window forfor robust robust y
Slide 27: Scanner Optimisation & Control enabled through Wafer Metrology & Computational Litho
ASML Scanner Optimisation & Control enabled through Wafer Metrology & Computational Litho Programmable Programmable Wavefront pupil and polarization Stages Illuminator Lens Sensors ators ipe scanner actu rec Computational CD and Overlay Wafer Lithography improvements Metrology ion Optimization Setup
Slide 28: Section Summary
Section Summary Low k1 Double Patterning Lithography enables extension of immersion Lithography bridging the gap until single patterning EUV is available However, Double Patterning presents significant Cost, Process Control, and Cycle Time manufacturing challenges Advanced Optical Metrology enables
Slide 29: Outlook and summary
Outlook and summary / Slide 29
Slide 30: Q2 2011 outlook
Q2 2011 outlook Order intake between € 900 million – €1 billion Net sales around € 1.5 billion Gross margin about 45% R&D at € 150 million SG&A at € 55 million ASML expects 2011 total revenue clearly above € 5 billion / Slide 30
Slide 31: Cash return
Cash return € 2.7B cash & cash equivalents at end Q1 2011 € 1 B / 24 month share buy back program in progress 21% of program executed until wk 19 7 million shares repurchased at an average price of € 29.66 Weekly updates available on ASML’s website Dividend for 2010 of € 0.40 per ordinary share (app
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