Cadence Design Systems, Inc. · NASDAQ:CDNS
Cadence Design Systems — DesignCon 2019 Conference and Expo
27 slides from Cadence Design Systems's conference presentation, 2019
Slide 1: Effect of Power Plane Inductance on Power Delivery Networks
Effect of Power Plane Inductance on Power Delivery Networks This session was presented as part of the DesignCon 2019 Conference and Expo For more information on the event, please go to DesignCon.com
Slide 2: Effect of Power Plane Inductance on Power Delivery Networks (PDNs)
Effect of Power Plane Inductance on Power Delivery Networks (PDNs) Shirin Farrahi, (Cadence) Ethan Koether (Oracle Corporation) Mehdi Mechaik (Cadence) Istvan Novak (Samtec) 2
Slide 3: Speakers
Speakers Shirin Farrahi Principal Software Engineer, Cadence shirinf@cadence.com Shirin Farrahi is a principal software engineer at Cadence working on the development of signal and power integrity tools. Prior to joining Cadence, she spent four years as a hardware engineer in the SPARC Microelectron
Slide 4: Power Plane Inductance
Power Plane Inductance Power plane inductance is important for PDN design – Impacts frequency response IC decap – Affects ground bounce noise Power return plane – Affects power network decoupling – Can be difficult to intuitively estimate Loop area Power plane loop inductance is Power plane nece
Slide 5: Net Inductance
Net Inductance Allegro workflow for quickly simulating net loop inductance at 1MHz Visualize return current on the Allegro canvas 5
Slide 6: Outline
Outline Hybrid simulator correlation – Impedance of ball grid array – Power plane loop inductance on a small IC test board – Power plane loop inductance on a large motherboard Impact of design variations on power plane loop inductance Loop inductance and coupling Conclusion 6
Slide 7: Hybrid Simulator – Sigrity PowerSI Technology
Hybrid Simulator – Sigrity PowerSI Technology Uses numerical methods and approximations to solve electromagnetic fields and extract S- parameters Impedance parameters are then extracted from the S-parameters and used to extract inductance quantities for several structures Measurement to simula
Slide 8: Hybrid Simulator – Sigrity PowerSI Technology
Hybrid Simulator – Sigrity PowerSI Technology Measurement to simulation correlation of ball grid array package is obtained 2” x 2” package size, unpopulated, 800μm core Excellent correlation between measurement and simulation of transfer impedance between Cadence® Sigrity™ PowerSI® 3D solver a
Slide 9: Correlation of Loop Inductance – Case 1: Small IC Test Board
Correlation of Loop Inductance – Case 1: Small IC Test Board Power plane loop inductance measurements on a small IC test board – Keysight E5061B VNA from 100kHz to 200MHz – Used S21 measurement to avoid measurement error with a one-port setup* – Power plane being measured/simulated on Layer 5 * No
Slide 10: Correlation of Loop Inductance – Case 1: Small IC Test Board
Correlation of Loop Inductance – Case 1: Small IC Test Board Power plane loop inductance measurements on a small IC test board – Keysight E5061B VNA from 100kHz to 200MHz – Common-mode toroid transformer used as a choke to suppress cable-braid loop error at low frequencies – Simulation done using
Slide 11: Correlation of Loop Inductance – Case 1: Small IC Test Board
Correlation of Loop Inductance – Case 1: Small IC Test Board Power plane loop inductance measurements on a small IC test board – Added capacitors to power plane 11
Slide 12: Correlation of Loop Inductance – Case 2: Large Motherboard
Correlation of Loop Inductance – Case 2: Large Motherboard Power plane loop inductance measurements on a large motherboard – 24 layers, two processors, and four PCIe® ports per processor – First version had noise coupling on PCIe lane due to nearby DC-DC converter* * Kocubinski, L, Blando, G, and
Slide 13: Correlation of Loop Inductance – Case 2: Large Motherboard
Correlation of Loop Inductance – Case 2: Large Motherboard Zoomed Layout Detail Photo of Wafer Probe Landing Power plane loop GND inductance measurements on a large motherboard 12V Input Pad – Probe configuration Wafer for power plane Probe measurement Landing Points DC-DC Converter Footprint 13
Slide 14: Correlation of Loop Inductance – Case 2: Large Motherboard
Correlation of Loop Inductance – Case 2: Large Motherboard Power plane inductance on first version of the Power plane inductance on final version of the motherboard, Blue = measured, orange = sim motherboard, Blue, yellow, and purple = measured, orange = sim 14
Slide 15: Impact of Design Changes on Power Plane Loop Inductance, Case 1 Variant
Impact of Design Changes on Power Plane Loop Inductance, Case 1 Variant Design variations: – Plane width port – Anti-pads -+ – Power vias – Ground vias – Decoupling capacitors – Power to ground short – Power to ground inductance Inductance values reported at 2MHz as seen by the sink with the sou
Slide 16: Impact of Plane Width on Power Plane Loop Inductance, Case 1 Variant
Impact of Plane Width on Power Plane Loop Inductance, Case 1 Variant Increasing plane width decreases loop inductance seen by sink Biggest change seen from 100mils to 500mils 16
Slide 17: Impact of Design Changes on Power Plane Loop Inductance, Case 1 Variant
Impact of Design Changes on Power Plane Loop Inductance, Case 1 Variant Anti-pad diameter must be very large to sink have a significant impact on loop inductance Also found that number of anti-pads and src location didn’t have a big impact on inductance Plane width 500mils, distance from sourc
Slide 18: Impact of Design Changes on Power Plane Loop Inductance, Case 1 Variant
Impact of Design Changes on Power Plane Loop Inductance, Case 1 Variant Increasing number of power vias near the sink source decrease loop inductance seen by the sink pwr vias Power vias connect to a power plane shape src on the surface 18
Slide 19: Impact of Design Changes on Power Plane Loop Inductance, Case 1 Variant
Impact of Design Changes on Power Plane Loop Inductance, Case 1 Variant Similar findings to impact of power vias More vias near source decrease loop inductance seen by sink 19
Slide 20: Impact of Number of Decoupling Capacitors on Power Plane Inductance
Impact of Number of Decoupling Capacitors on Power Plane Inductance Removing each decoupling capacitor increased power plane loop inductance Biggest impact when removed last decoupling capacitor between plane and ground sink 1μF 0.01μF 0.1μF 1μF 1μF All capacitors populated 47μF 22μF 1μF src
Slide 21: Impact of Design Changes on Power Plane Loop Inductance, Case 1 Variant
Impact of Design Changes on Power Plane Loop Inductance, Case 1 Variant sink Power to ground via short moved from near source to near sink short Inductance increases as short gets further src from sink 21
Slide 22: Impact of Design Changes on Power Plane Loop Inductance, Case 1 Variant
Impact of Design Changes on Power Plane Loop Inductance, Case 1 Variant Via short now replaced with a ground via connected to power plane by 1nH inductor to mimic decoupling capacitor As before, loop inductance increased as sink inductor got further from sink 1nH src 22
Slide 23: Loop Inductance and Coupling, Case 2
Loop Inductance and Coupling, Case 2 Mid-frequency noise from a DC-DC converter to a PCIe® lane required two re- spins to resolve Final version of board had more ground vias near victim and moved decoupling capacitors to top of board * Kocubinski, L, Blando, G, and Novak, I., “Mid-Frequency Nois
Slide 24: Loop Inductance and Coupling, Case 2
Loop Inductance and Coupling, Case 2 Change in coupling (S21) due to board design changes well captured by simulation 24
Slide 25: Conclusions
Conclusions Power plane loop inductance is important for PDN frequency response and for understanding a design’s ground bounce noise and noise coupling Our hybrid simulation approach provides an efficient method of estimating power plane loop inductance and coupling due to inductive effects Im
Slide 26: Acknowledgements Questions?
Acknowledgements Bradley Brim, Cadence Design Systems Gustavo Blando, Samtec Questions? 26
Slide 27: Cadence trademark notice
© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. Accellera and SystemC are trademarks of Accellera Systems Initiativ
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