ASML Holding NV · EURONEXT:ASML
ASML Holding NV — Deutsche Bank Access Asia Conference 2010
56 slides from ASML Holding NV's conference presentation, May 12, 2010
Slide 1: Leadership Through Innovation – Litho for the future
Leadership Through Innovation – Litho for the future Deutsche Bank Access Asia Conference 2010 Singapore Craig De Young VP Investor Relations and Corporate Communications May 12, 2010 Public
Slide 2: Safe Harbor
Safe Harbor "Safe Harbor" Statement under the US Private Securities Litigation Reform Act of 1995: the matters discussed in this document may include forward-looking statements, including statements made about our outlook, realization of backlog, IC unit demand, financial results, average selling pr
Slide 3: Agenda
Agenda ASML Overview Technology Leadership Critical Mass through Integrated Network The Sustainable Semiconductor Industry The Lithography Roadmap Market/ASML Update Slide 3 | Public
Slide 4: ASML: Leading supplier of lithography equipment to the semiconductor industry
ASML : Leading supplier of lithography equipment to the semiconductor industry Headquarters: Veldhoven, The Netherlands Market Cap approx € 10 B Slide 4 | Public
Slide 5: ASML's growing market share
ASML’s growing market share 7,000 70% 70% WW M$ 6,000 60% ASML Revenue Market Share [%] ASML market share World Wide Market [M USD] 60% 5,000 50% 50% 4,000 40% 40% 3,000 30% 30% 2,000 20% 20% 1,000 10% 10% 0 0% 0% 1990 2000 1991 1994 1995 1998 1999 2002 2003 1980 1981 1982 1983 1984 1985 1986 1987 1
Slide 6: ASML: #2 semiconductor equipment supplier with approx. 6500 employees worldwide
ASML: #2 semiconductor equipment supplier with approx. 6500 employees worldwide 19% 5% sales 76 % sales ASML employees ASML employees ASML employees in US: 1,470 in Europe: 3,800 in Asia: 1,327 Over 60 sales and service offices located worldwide Source: ASML Q4, 2009 Slide 6 | Public
Slide 7: Semiconductor food chain 2010 Forecast
Semiconductor food chain 2010 Forecast Source: Gartner Dataquest & VLSIResearch & ASML Hynix Micron TSMC Capex € 22 B Semiconductor Fab equipment sales € 204 B Tokyo € 17 B Electron Litho € 4.4 B Semiconductor sales 280 B Applied Materials ASML Samsung Canon ASML > € 3.4B* KLA- Nikon Intel Tencor LA
Slide 8: Agenda
Agenda ASML Overview Technology Leadership Critical Mass through Integrated Network The Sustainable Semiconductor Industry The Lithography Roadmap Market/ASML Update Slide 8 | Public
Slide 9: Enabling Moore's Law towards nm resolution
Enabling Moore’s Law towards 10 nm resolution Lithography supports shrink roadmap 200 Logic DRAM NAND Resolution/half pitch, "Shrink" [nm] 100 80 ARF AT:1200 60 XT:1400 50 XT:1700i 40 ARFi XT:1900i 30 NXT:1950i NXE:3100 20 EUV NXE:3300 ’02 ’03 ’04 ’05 ’06 ’07 ’08 ’09 ’10 ’11 ’12 ’13 ’14 ’15 Year of
Slide 10: The drive (Moore)… the way (Rayleigh)
The drive (Moore)………the way (Rayleigh) Moore's Law - 1969 Rayleigh’s Equation - 1896 Gordon Moore Lord Rayleigh The capacity of each new chip λ CD = k1 * doubles every 18-24 months NA • reduce wavelength Critical Dimension (CD) • increase NA shrinks 30% each generation • lower k1 Slide 10 | Public
Slide 11: Wavelength down, NA up to meet customer needs
Wavelength down, NA up to meet customer needs 200 248 nm DRAM Logic NAND Flash (working memory (microprocessors, (special memory, in PC’s) the “brains” used in, for example of PC’s) mp3 players) Resolution, "Shrink" (nm) 100 80 193 nm 60 50 40 Technology transitions 30 20 EUV 13.5nm ’02 ’03 ’04 ’05
Slide 12: Other critical parameters in Lithography
Other critical parameters in Lithography Lithography determines dimensions and overlay Imaging 1/1,000 mm How small can you print Lowest cost per chip Overlay Productivity How accurate can you print How fast can you print Slide 12 | Public
Slide 13: Lithography is the motor of the semiconductor industry
Lithography is the motor of the semiconductor industry In 30 years: Resolution from > 1,200 nm to < 20 nm System prices from <0.5M€ per system to >60M€ 13.5nm 193nm 248nm 365nm 436nm 2010’s NXE EUV systems 2000’s Resolution: 32 to <20 nm NXT:Twinscan overlay: 2 nm 1990’s Resolution: PAS 5500 100 to
Slide 14: ASML Market Share (revenue)
Market share gained by delivering ArFi technology in time 12” & ArF 60% • Timely introduction KrF & Step & Scan ASML Market Share (revenue) 50% • Reliable introduction • Cost effective 40% 8” & i-line 30% 6” & early i-line 20% 10% 0% 1985 1990 1995 2000 Time Source: ASML, SEMI Slide 14 | Public
Slide 15: Agenda
Agenda ASML Overview Technology Leadership Critical Mass through Scale and an Integrated Network The Sustainable Semiconductor Industry The Lithography Roadmap Market/ASML Update Slide 15 | Public
Slide 16: Cost of Technology
Cost of Technology 5500 5500 TWINSCAN TWINSCAN Platform PAS5000 stepper R&D scanner ArF dry ArF wet EUV R&D 50 M€ 125 M€ 250 M€ 500 M€ 1,000 M€ 1,500 M€ Required 333 M€ 850 M€ 1,700 M€ 3,500 M€ 6,500 M€ 10,000 M€ Revenue Average Selling 1 M€ 3 M€ 7 M€ 16 M€ 35 M€ 60 M€ Price Required 350 number NNum
Slide 17: Commitment to innovation requires a strong player with scale
Commitment to innovation requires a strong player with a certain scale (gained though market share) R& D spend supports continued technology leadership ASML R&D investment (excl. Zeiss for lenses) 4000 550 500 3500 450 3000 400 R&D Investment (M€) Total Sales (M€) 2500 350 300 2000 250 1500 200 1000
Slide 18: Internal resource spending less than half of total R&D
Internal resource spending less than half of total R&D R&D expenses 2009 Expected R&D expenses 2014 Farm out (TNO, TU's, others) Cymer 15% Carl Zeiss Carl Zeiss 7% 18% 18% Philips, VDL and others Farm out (TNO, 10% Cymer TU's, others) 9% 7% labor Philips, VDL 4% and others 47% ASML companies 6% 9% B
Slide 19: ASML and its network has a highly trained workforce
ASML and its network has a highly trained workforce ● 49% of personnel have Advanced Degrees, of which approximately 200 PhD’s ● 33% of personnel has Bachelor as highest degree ● R&D: >1,800 payroll + >900 contracted ● Integrated knowledge network: approximately another 20,000 jobs More than 600 sup
Slide 20: Integrated knowledge network essential for success
Integrated knowledge network essential for success OEM partners providing R&D Partners key sub systems (our virtual research lab) Wafer scanner Resist Track Masks Others Semiconductor device manufacturers Slide 20 | Slide 20 | Public
Slide 21: Top spenders are ASML customers
Top 20 spenders are ASML customers - they invest approx. 80% of industry capex Slide 21 | Public
Slide 22: Agenda
Agenda ASML Overview Technology Leadership Critical Mass through Integrated Network The Sustainable Semiconductor Industry The Lithography Roadmap Market/ASML Update Slide 22 | Public
Slide 23: Communication became ~10^13 more energy efficient
Communication became ~ 1013 more energy efficient enabled by scaling of semiconductors 5 MJ/b 20 wood sticks of 2 cm diameter and 50 cm long equals ~3 dm³ Message size 10 characters or 10 ~15 MJ/dm³ energy from burning wood we use 45 MJ/message or 5 MJ/b Frederic Remington, “The Smoke signal”, 1905,
Slide 24: Less energy to use a bit
Less energy to use a bit Computations per Kilowatt hour double every 1.5 years 2008 + 2009 laptops 1.E+16 SiCortex SC5832 1.E+15 Dell Dimension 2400 1.E+14 Gateway P3. 733 MHz 1.E+13 Dell Optiplex GXI IBM PS/2E + Sun SS1000 1.E+12 486/25 and 486/33 Desktops 1.E+11 IBM PC Computations per kWh 1.E+10
Slide 25: Total energy to create the smallest chip function
Total energy to create the smallest chip function Total energy bill per memory bit continues to fall sharply with introduction of EUV 1000 μJ / bit ] Energy used to produce a memory bit [μ NAND 100 Introduction of EUV 10 1 70 60 50 40 30 20 10 0 Technology node [nm] Slide 25 | Public
Slide 26: Litho investment per transistor decreases
Litho investment per transistor decreases Litho cost falls 2.1% point/year faster than IC revenues per transistor IC Revenue & Lithography investments per trillion transistors 10,000,000 CAG 1,000,000 R: - 39,2 % [USD per tr. transistors] 100,000 CAG R: - 41,3 % 10,000 IC revenue per tr. Transisitor
Slide 27: Consumers are the winners
Consumers are the winners 10000 $2,305 for 1Gigabyte (GB) 1000 100 $/GByte 10 1 $0.17 for 1 GB 0 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 Note: data iSupply, March 2009. High quality Flash Slide 27 | Public
Slide 28: Agenda
Agenda Technology World Leadership in Europe Critical Mass in Manufacturing through Integrated Network The Sustainable Semiconductor Industry The Lithography Roadmap Market/ASML Update Slide 28 | Public
Slide 29: An accelerated roadmap forces litho complexity
An accelerated roadmap forces litho complexity Lithography supports shrink roadmap 200 DRAM Logic NAND Flash (working memory (microprocessors, (special memory, in PC’s) the “brains” used in, for example mp3 players) of PC’s) Resolution/half pitch, "Shrink" [nm] 100 80 ARF AT:1200 60 XT:1400 50 XT:17
Slide 30: Litho challenges and likely lithographic options
Litho challenges and likely lithographic options Most likely Opportunity k1 = (half-pitch) * numerical aperture / wavelength Challenge Half pitch (nm) 100 65 45 32 22 16 11 Year 2005 2007 2009 2011 2013 2015 λ (nm) NA 248 0.93 0.34 Double (Double) patterning, DP: CoO challenge 193 0.93 0.31 DP, k1 >
Slide 31: Likely lithographic options
Likely lithographic options Most likely Opportunity k1 = (half-pitch) * numerical aperture / wavelength Challenge Half pitch (nm) 100 65 45 32 22 16 11 Year 2005 2007 2009 2011 2013 2015 λ (nm) NA 248 0.93 0.34 Double (Double) patterning, DP: CoO challenge 193 0.93 0.31 DP, k1 > 0.125 DP², k1 > 0.06
Slide 32: ASML's R&D focus is on three strategic programs
ASML’s R&D focus is on three strategic programs TWINSCAN NXT Holistic Lithography EUV Slide 32 | Public
Slide 33: TWINSCAN NXT:1950i – ArFi Immersion Scanner
TWINSCAN NXT:1950i – ArFi Immersion Scanner for Double Patterning 30nm and smaller • Productivity more than 175 wafers per hour • Overlay less than 3 nm Slide 33 | Public
Slide 34: ASML Immersion Extendable Product Roadmap
ASML Immersion Extendable Product Roadmap improved CD and overlay control at > 200 W/hr productivity Available Available Available Q4-2010 Q4-2011 XT:1900Gi XT:1950Hi NXT:1950i NXT:1950i+PEP NXT:1950i+EXT Resolution 40 nm 38 nm 38 nm 38 nm 38 nm CDU <1.5 nm <1.5 nm <1.1 nm <1.1 nm <0.8 nm Overlay (S
Slide 35: Holistic Litho provides a window to shrink
Holistic Litho provides a window to shrink Process Window Process Control Pre-production: enlarges the process window further and earlier through pattern optimization and scanner tuning Production: ensures that the process stays in the “sweet spot” of the process window maximized for the specific ap
Slide 36: Holistic Litho – Addressing process control
Holistic Litho – Addressing process control To keep process in application specific window center using computational lithography, cost effective metrology and feedback loops Scanner settings Data design/ SMO Scanner Wafer data mask data FlexRay settings BaseLiner Control Tuning Wafer data Scanner s
Slide 37: EUV for 22nm and beyond
EUV for 22nm and beyond – pilot systems to ship starting in H2 2010 with volume production tools in 2012 Machine design changes ● Mirror optics and wafers in vacuum ● Moving stages in vacuum ● New type of light source Slide 37 | Public
Slide 38: EUV Lithography: getting the light through
EUV Lithography: getting the light through Only 68% of the light will reflect from every mirror (maximum = 72%) scattering Mirror 0.3nm Mirror Flatness: Mirror 1mm over 1000 km 30cm Slide 38 | Public
Slide 39: EUV Lithography: positioning of the light
EUV Lithography: positioning of the light EUV mirror system 0 km 500 38 Mirror positioning 0,03 nm Overlay tolerance mirror: 0,1 nm Focus tolerance mirror: 25 nm Design Slide 39 examples | Public
Slide 40: EUV - next generation lithography
EUV - next generation lithography First NXE:3100 systems planned to ship in H2 2010 6th order received confirms appetite from all semiconductor sectors Slide 40 | Public
Slide 41: EUV is the only feasible litho technology for foundries
EUV is the only feasible litho technology for foundries Enabling cost effective shrink without design restriction 2.5 DP, Double Patterning, DP EUV good shrink, cost too high DDL,and design Double Dipole 2.0 restrictions. Lithography, Extreme Relative litho cost per wafer low k1 imaging at DDL relax
Slide 42: Litho costs back to normal with EUV
Litho costs back to normal with EUV >100 W/hr 3.5 DPT case, Litho cost EUV case, Litho cost increases 2 ~ 3 times trend returns 3 Litho cost per wafer [a.u.] 2.5 2 1.5 1 0.5 1st Gen. 2st Gen. DTP DTP 0 KrF set 1400 set 1900i set 1900i DPT 1900i DPT EUV EUV 100W/hr 180W/hr Source Samsung, Prague, oct
Slide 43: TWINSCAN EUV Product Roadmap
TWINSCAN EUV Product Roadmap Source roadmap in place for immersion compatible productivity 2006 2010 2012 2013 Demonstration NXT:3100 NXE:3300B NXE:3300C tool Resolution 32 nm 27 nm 22 nm 16* nm NA / σ 0.25 / 0.5 0.25 / 0.8 0.32 / 0.2-0.9 0.32 / OAI Overlay (SMO) < 7 nm < 4.5 nm < 3.5 nm < 3 nm Thro
Slide 44: Extendibility of EUV down to sub nm possible
Extendibility of EUV down to sub 5 nm possible increasing apertures up to 0.7, wavelength reduction down to 6.8 nm using 13 nm compatible optics with depth of focus as the major challenge 40 0.8 35 0.7 Resolution, Depth of focus [nm] 30 0.6 k-factor, Aperture 25 0.5 Resolution DOF@13 nm 20 0.4 DOF@6
Slide 45: Summary
Summary ● Semiconductor technology proliferation in all products has been fueled by the reduction of: ● energy used by devices ● energy to create devices ● cost to execute a calculation cycle or store/read a bit ● The cost of lithography relative to chip revenues is falling ● The model of a cooperat
Slide 46: Agenda
Agenda Technology World Leadership in Europe Critical Mass in Manufacturing through Integrated Network The Sustainable Semiconductor Industry The Lithography Roadmap Market/ASML Update Slide 46 | Public
Slide 47: Semiconductor revenue outlook increases
Semiconductor revenue outlook increases 21% revenue growth, 15% IC unit growth* 2010 Semiconductor revenue growth forecast over time 30% YoY Semiconductor revenue growth Future Horizons 25% SIA Semico 20% Dataquest IC Insights 15% [%] WSTS iSuppli 10% VLSI Research AVERAGE 5% 0% May-10 Mar-10 May-09
Slide 48: IC inventories appear under control
IC inventories appear under control as measured by days of inventory 3mma IC unit sales, inventory and inventory days 25 monthly IC inventory based on 3mma IC ASPs 120 3mma IC unit sales / Inventory [Bio. Units] 3mma IC unit sale 3mma IC unit sales corrected for inventory Inventory days (right axis)
Slide 49: Memory output capacity below 2008 peak by end 2010
By end 2010 memory output capacity is estimated to be more than 10% below peak capacity of 2008 Memory WW wafer output split by wafer size and node 6x & 5x Estimate 30 & f 2600 0m ab Conversion m c lo 2400 Immersion for 5x, 4x ut s & 3x conversion ili ur Starts / Month [300mm equiv. KWspM] 2200 sa e
Slide 50: Leading Edge Memory Drives Backlog
Leading Edge Memory Drives Backlog Total value M€ 2,170 Technology KrF 9% 51% NXT 39% XT i-line 1% ArF Region immersion End-use 90% USA Japan 11% 19% Singapore 6% IDM Taiwan 14% 31% Europe 3% Memory Foundry China 7% Korea 75% 11% 23% Numbers have been rounded for readers’ convenience Slide 50 | Publ
Slide 51: Bookings activity by sector
Bookings activity by sector - Total value € 1,004 M Q1 bookings are driven by DRAM with NAND order activity starting Foundry and IDM’s ordering for capacity expansion Bookings in value Bookings in units Memory 79% Memory 48% Foundry 14% Foundry 30% IDM 7% IDM 22% Slide 51 | Public
Slide 52: DRAM bit sufficiency analysis
DRAM DRAM bit sufficiency analysis: At 47% bit demand growth market is slightly under-supplied during 2010 DRAM Sufficiency Model: ASML's fcst-based Supply versus Gartner-based Demand 700 140% ASML Modeled DRAM bit supply [Mio. GB] Gartner Forecast DRAM bit demand [Mio. GB] 600 DRAM Sufficiency (ASM
Slide 53: NAND bit sufficiency analysis
NAND NAND bit sufficiency analysis: At 70% bit demand growth market is well balanced for 2010 NAND Sufficiency Model: ASML's fcst-based Supply versus Gartner-based Demand 4,000 160% ASML Modeled NAND bit supply [Mio. GB] Gartner Forecast NAND bit demand [Mio. GB] 3,500 140% NAND Sufficiency (ASML) 3
Slide 54: 2010 outlook
2010 outlook Q2 Net sales expected around € 1 billion Q2 bookings are expected at similar level as in Q1 2010 (€ 1,004 M) We expect this cycle to be sustained by the normal technology transitions of the early adopters, the subsequent technology conversions by second tier DRAM makers, the next Flash
Slide 55: Summary
Summary • ASML has gained required scale through market gains supporting required litho R&D investments • ASML is leading in meeting the industry's shrink roadmaps • Memory supply/demand close to balance in 2010. Bits growth supplied by shrink only • Further memory bit supply growth in near future w
Slide 56: Public
Slide 56 | Public