Arteris, Inc. · NASDAQ:AIP

Arteris — Technical Presentation (October 2022)

25 slides from Arteris's technical presentation, Oct 20, 2022

Slide 1: FMEDA Automation for Scalability and Reuse in Complex System on Chips
FMEDA AUTOMATION FOR SCALABILITY AND REUSE IN COMPLEX SYSTEM ON CHIPS A P P L I C AT I O N O F S O T I F & I S O 2 6 2 6 2 O C TO B E R 2 0 TH, 2 0 2 2 FRANK SCHIRRMEISTER STEFANO LORENZINI VP Solutions & Business Development Fellow and Functional Safety Manager franks@arteris.com
Slide 2: Agenda
Agenda 1 Arteris Overview 2 What is SoC System IP? 3 Safety in SoC IP - Networks-on-Chip Example 4 How to Deal with Safety & FMEDA Holistically? 5 Summary & Outlook October 20th 2022 Copyright © 2022, Arteris 2
Slide 3: Cars Become Data Centers on Wheels
Cars Become Data Centers on Wheels CAR COMPETENCIES TURN FROM MECHANICAL TO SOFTWARE AND ELECTRONICS Source: Visteon Corporation 2019 ECU Consolidation into 4 main zones: 1. ADAS/Car Controller zone 2. Cockpit zone 3. Chasis/Motor/Engine zone 4. Connectivity zone Advanced Interconnect Enables Novel
Slide 4: Arteris IP – The Leading SoC System IP Company
Arteris IP – The Leading SoC System IP Company FOUNDED IN 2013, GLOBAL, PUBLIC Data as of December 31, 2021 System IP Leader Diversified Customer Base Proven Customer Successes Publicly Disclosed Customers • Pioneer of networking IPs for SoCs • 550+ SoC design starts • Leader in IP deployment softwa
Slide 5: SoC System IP Enables SoCs
SoC System IP Enables SoCs Arteris NoC Interconnect IP Arteris IP Deployment Software • SoCs allowed to make decisions are Protocol converters, switches, rate adaptors, etc. SoC IP blocks packaged with Arteris IP deployment software much more complex than data processing SoCs • Creates the connectio
Slide 6: Arteris IP Accelerates SoC Creation
Arteris IP Accelerates SoC Creation • During Specification & Integration, the SoC is a virtual object described in XML, using the IP-XACT standard – Accelerates IP deployment – Automates documentation & traceability – Whole solution → IP assembly methodology • During Architecture & NoC RTL Assembly,
Slide 8: Arteris IP Network-on-Chip Supports Advanced Architectures
Arteris IP Network-on-Chip Supports Advanced Architectures LOWERING R&D & UNIT COSTS THROUGH ADVANCED FEATURES, AUTOMATION & LEADING PPA • Performance: Up to 2 GHz frequency @16nm, >2TBit/sec bandwidth with 1024-bit links PERFORMANCE AREA • Power: <0.5 mW idle power/1M gates @16nm, 0-cycle unit-leve
Slide 9: Example Interconnect Safety Capabilities
Example Interconnect Safety Capabilities Initiator Initiator Initiator Initiator • Unit Duplication & Checker Modules IP IP IP IP • Fault in Network Interface Units, Firewalls, & Power Disconnect modules • Parity Code in Packet ECC/P ECC/P ECC/P ECC/P • Fault in Buffers, Pipes, Width Converters, Ser
Slide 12: FMEDA Creation Challenges
FMEDA Creation Challenges Configurability Reusability Scalability • IPs become more and more configurable, • The same way RTL models are reused, existing • Modern SoCs integrate dozens of different IPs, exposing many HW params options to the user FMEDA data could too each coming with their own FMEDA
Slide 13: Configurability – The Challenge
Configurability – The Challenge FMEDA IS A MANUAL TABLE-ORIENTED PROCESS IP A The The IP IP is reconfigured is reconfigured adding adding relevant features functions other and removing P1 SP1 SPFM / LFM FMEDA IP A DESIGN HIERARCHY FM DESCRIPTION FM EFFECT S/R SAFETY NECHANISM Fs% Dfm % Kfmc,rf% Kfmc
Slide 14: Reusability – The Challenge
Reusability – The Challenge FMEDA IS A MANUAL TABLE-ORIENTED PROCESS IP B IP B is derived from blocks of IP A (reuse) P1 SP1 SPFM / LFM FMEDA IP B DESIGN HIERARCHY SP1 SP2 SP2 P1 SP2 P2 SP3 P2 SP3 October 20th, 2022 Copyright ©, 2022, Arteris 14
Slide 15: Configurability & Reusability – The Need
Configurability & Reusability – The Need REPLACE THE TABLE-ORIENTED PROCESS WITH A MODEL-ORIENTED APPROACH Design Hierarchy (HW model instances) HW Models Library Safety Models Library SAFETY MODEL ▪ Reference to an HW Model ▪ Miss Behavioral description IP A ▪ Safety Data (including design data est
Slide 16: Scalability – The Challenge
Scalability – The Challenge SOC FMEDA IS A MANUAL AGGREGATION OF MANY IP FMEDA ~250FMs / IP Aggregation of tens of heterogeneous IP FMEDA formats ~12500FMs Readability of the SoC FMEDA (become thousands of lines) FMEDA Integration with System FMEDA SYSTEM October 20th, 2022 Copyright ©, 2022, Arteri
Slide 17: Scalability – The Need
Scalability – The Need FM1 REPLACE THE MANUAL AGGREGATION PROCESS WITH AUTOMATION TLFM FM2 IP SoC FMEDA Generator ABSTRACTION IP FMEDAs Import ▪ IP FMEDAs semantic recognition and data alignment Smart IP FMEDA Import TRACEABILITY AGAINST OTHER WPs ▪ IP FMEDAs import SoC FMEDA Generation ▪ IP FMEDAs
Slide 18: FMEDA Traceability – The Need
FMEDA Traceability – The Need TRACE SAFETY ANALYSIS EVOLUTION DURING THE LIFE CYCLE EXECUTION • FMEDA is tightly connected with the actual design. Traceability against requirements and specs is required during the different phases (horizontal traceability). Change • Being able to link FMEDA, and oth
Slide 20: Summary: Proposed Process
Summary: Proposed Process • Complex Automotive SoC requires improving FMEDA FMEDA CREATION productivity during the steps of the design. CHALLENGES • High IP configurability requires automation to create IP FMEDA according to the actual HW configuration. Configurability Reusability Scalability • FMED
Slide 22: Traceability: Interested in More Discussion?
Traceability: Interested in More Discussion? • FMEDA is tightly connected with the actual design. Arteris® Harmony Trace™️ Traceability against requirements and specs is required during the different phases (horizontal traceability). Change • Being able to link FMEDA, and others type of safety analy
Slide 25: Thank you!
Thank you! FRANK SCHIRRMEISTER STEFANO LORENZINI VP Solutions & Business Development Fellow and Functional Safety Manager franks@arteris.com

Arteris — Technical Presentation (October 2022) on 6ix

Arteris — Technical Presentation (October 2022)

Slide 1: FMEDA Automation for Scalability and Reuse in Complex System on Chips

Slide 2: Agenda

Slide 3: Cars Become Data Centers on Wheels

Slide 4: Arteris IP – The Leading SoC System IP Company

Slide 5: SoC System IP Enables SoCs

Slide 6: Arteris IP Accelerates SoC Creation

Slide 7: What about Safety in SoC IP?

Slide 8: Arteris IP Network-on-Chip Supports Advanced Architectures

Slide 9: Example Interconnect Safety Capabilities

Slide 10: How to Deal with Safety & FMEDA Holistically?

Slide 11: Safety Throughout the Value Chain

Slide 12: FMEDA Creation Challenges

Slide 13: Configurability – The Challenge

Slide 14: Reusability – The Challenge

Slide 15: Configurability & Reusability – The Need

Slide 16: Scalability – The Challenge

Slide 17: Scalability – The Need

Slide 18: FMEDA Traceability – The Need

Slide 19: Summary & Outlook

Slide 20: Summary: Proposed Process

Slide 21: Further Reading: FMEDA Generation Process

Slide 22: Traceability: Interested in More Discussion?

Slide 23: Traceability: Interested in More Discussion?

Slide 24: Traceability: Interested in More Discussion?

Slide 25: Thank you!