Synopsys, Inc. · NASDAQ:SNPS

Synopsys — Design Automation Conference 2006

10 slides from Synopsys's conference presentation, Jul 24, 2006

  1. Slide 1: Application of IC Compiler on a Mobile & Communication Chip

    Application of IC Compiler on a Mobile & Communication Chip For Integration of Timing, Low Power and Yield Centric Flow Mutsunori Igarashi Manager, Design Methodology Department II Toshiba Corporation Semiconductor Company 24th July 2006 Design Automation Conference 1 Copyright © 2006 Toshiba Corpor

  2. Slide 2: Agenda

    Agenda • Challenges of Physical Implementation • Mobile & Communication Applications • “TC90515XBG” for Home Digital Network • “TC90515XBG” Implementation With IC Compiler • Implementation Flow • Results • Summary and Next Steps Semiconductor Company 2 Copyright © 2006 Toshiba Corporation. All right

  3. Slide 3: Challenges of Physical Implementation

    Challenges of Physical Implementation • Design manufacturability constraints are increasing from 90nm onwards • 65nm~ designs require tradeoffs between timing, power and yield 45nm Methodology Lithographic getting complex Defect Check & Correction Feature Size Variation Pattern Based Defect Critical

  4. Slide 4: Mobile & Communication Applications

    Mobile & Communication Applications • Home wireless LAN systems are becoming more and more prevalent • Stable HD-A/V wireless transmission with secure contents protection is becoming a reality Network Server FPD,LCD 802.11a/e RD(UAV) Camera 802.11a/e HDD Living Cellular TC90515XBG 802.11b/g in it PD

  5. Slide 5: TC90515XBG for Home Digital Network

    TC90515XBG for Home Digital Network • Compilable Dual Core for Hi-performance and Low Power at Less Cost ƒ Chip size reduction by 60%, and power reduction by 50% from “505” Performance TX49 (240MHz) Dual Processor High Performance Next 802.11a/e/h/i ( MeP X 2 ) 802.11a/b/g/e/h/i Generation DTCP, PCI

  6. Slide 6: TC90515XBG Implementation with IC Compiler

    TC90515XBG Implementation with IC Compiler TC90515XBG Dual MeP Core 90nm, 2.5M gates, 2.8Mbit memory IC Compiler Addressed Our Challenges 200/80 MHz, 1.2V/2.5V/3.3V • Global optimization of timing, power Power Dissipation < 500 mW and area ƒ IC Compiler’s integrated solution resolves high level trad

  7. Slide 7: Implementation Flow

    Implementation Flow RTL w/Memory BIST, JTAG Synthesis Synthesis(DC, (DC,PwC, PwC,DFTCMAX) DFTCMAX) Compile w/low Vth cells Floorplanning (ICC) Compile w/low Vth cells Clock Gating (per 16bit) Clock Gating (per 16bit) Adaptive SCAN (Stuck at/Trans (PLL)) Adaptive SCAN (Stuck at/Trans (PLL)) IR Drop A

  8. Slide 8: Results (1/2)

    Results (1/2) •Quality of Results ICC vs PT path delay correlation ƒ Timing 12.5 • Good timing QoR with multi-mode optimization 12.0 P T p a th d e la y (c lo c k d e la y • Excellent timing correlation between 11.5 IC Compiler and PrimeTime in c lu d e d ) 11.0 ƒ Power 10.5 • Using Multi-Vth librar

  9. Slide 9: Results (2/2)

    Results (2/2) • Accelerated Time to Results ƒ IC Compiler could handle the complex design • (i.e. clock structure) ƒ The good timing correlation and the multi-mode optimization accelerated to reduce TAT • Ease of use ƒ Easy to adopt the adoptive SCAN into the design flow • GUI analysis and debugging

  10. Slide 10: Summary and Next Steps

    Summary and Next Steps z TC90515XBG tapeout scheduled for early August ’06 z IC Compiler delivered on very tight area, timing and power budgets z Reduced TAT using multi-mode optimization z Toshiba has several ongoing production designs with IC Compiler across different groups z Will require using s

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