Kulicke And Soffa Industries, Inc. · NASDAQ:KLIC
Kulicke And Soffa Industries — Technical Presentation (December 2003)
19 slides from Kulicke And Soffa Industries's technical presentation, December 2003
Slide 1: Characterization of Packaging Compatibility of Cu-Low K Interconnect
Characterization of Packaging Compatibility of Cu-Low K Interconnect Tony Pan(1), Jamin Ling(2,3), Jon Brunner(4), Frank Keller(4), George Carson(5), Renzhe Zhao(5), Tom Strothmann(3), (1) Applied Materials, Santa Clara, CA (2) currently ST Assembly, Testing, Services (STATS-US), Phoenix, AZ (3) K&S
Slide 2: Outline
Outline • Introduction • Packaging Low-k Dielectric Considerations • Low-k (Black Diamond) Wire Bonding Evaluation – Test Vehicle / Bond Pad Structure – Wire Bond Optimization (DOE) – Results – Conclusions • Low-k (Black Diamond) Flip Chip Evaluation – Test Vehicle – Solder Bumping Compatibility – F
Slide 3: Introducing Cu interconnect
Introducing Cu interconnect 500nm technology 3200 2800 2400 Cu-Low κ Clock Freq. (MHz) Al-Low κ 2000 1600 Cu-SiO2 1200 Al-SiO2 800 130nm technology 400 0 250 180 150 130 100 70 50 240 190 140 90 40 Technology Min. Feature (nm) Logic Depth = 12 Gates Ref. 1999 ACM/IEEE International Workshop on Timin
Slide 4: Low K Wafer Packaging - Challenges
Low K Wafer Packaging - Challenges Wafer Backgrinding, Applied Stress of ILD ¾ No or Low Stress Lamination / Delamination Process is recommended. Dielectric Wafer Sawing , Dielectric Peel-Off peeling off ¾ Appropriate sawing street structure necessary Source: K&S (Semicon 2003) ¾ Double Cut is r
Slide 5: Agenda
Agenda • Introduction • Packaging Low-k Dielectric Considerations • Low-k (Black Diamond) Wire Bonding Evaluation – Test Vehicle / Bond Pad Structure – Wire Bond Optimization (DOE) – Results – Conclusions • Low-k (Black Diamond) Flip Chip Evaluation – Test Vehicle – Solder Bumping Compatibility – Fl
Slide 6: Black Diamond Wire Bond - Bond Pad Stack
Black Diamond Wire Bond - Bond Pad Stack “L” Type “R” Type (Peripheral Via) (Central Via) Al Pad Oxide Al Pad Type 1,2 & 3 Single Low-k / FSG M2 / V1 Layer Cu / Low-k (1,2,4,5) Cu / FSG (3 ) M1 Low-k Type 4 1 Extra Low-k Layer Low-k Type 5 2 Extra Low-k Layers Oxide Silicon 6 IMAPS Packaging Cu /low
Slide 7: Black Diamond Wire Bond - Design Experiment
Black Diamond Wire Bond - Design Experiment • Primary Parameters: • Constant Velocity (C/V) 0.15 - 0.25 mil/ms • Ultrasonic Power 55 - 65 mAmp C/V Ultr.Pwr Force Pre-bleed • Bonding Force 8 - 14 gmf • Pre-Bleed (Power) 0 - 30%power (mil/msec) (mA) (gram) (% Pwr) + + + + • DOE: + + + - • 4 factor, 2
Slide 8: Black Diamond Wire Bond - Wire Bond Pull Test
Black Diamond Wire Bond - Wire Bond Pull Test Top of Loop Mid-Span Mid-Span Pull Geometry Top of Loop Bond pad in tension Bond pad in tension Pull Geometry across entire area and compression Wire Profile (as bonded) 8 IMAPS Packaging Cu /low-k Workshop San Diego, CA Dec 2003
Slide 9: Black Diamond Wire Bond - Modeling
Black Diamond Wire Bond - Modeling Capillary Bonded Ball Bond Pad (under USG Force) Low-k Layer(s) • Maximum shear strain for the three layer case is 20% lower SiO2 then the single low-k layer Silicon device for the same bonding force and USG Power. • This is due to the increase in compliance from t
Slide 10: Black Diamond Wire Bond - Experiment Results
Black Diamond Wire Bond - Experiment Results # of zero-failure in peeling Optimized Pad Structure Conclusions Significance Analysis per DOE Results • Bond Pad Structure is a determining factor for wire bond /low-k dielectric integrity • Ultrasonic Power and Bond Force are significant factors in wire
Slide 11: Agenda
Agenda • Introduction • Packaging Low-k Dielectric Considerations • Low-k (Black Diamond) Wire Bonding Evaluation – Test Vehicle / Bond Pad Structure – Wire Bond Optimization (DOE) – Results – Conclusions • Low-k (Black Diamond) Flip Chip Evaluation – Test Vehicle – Solder Bumping Compatibility – Fl
Slide 12: Cu / low-k Considerations - Flip Chip
Cu / low-k Considerations - Flip Chip • Considerations – Cu / low-k solder bumping capability – Cu / low-k test vehicle for backend assembly characterization and reliability – select / identify suitable range of underfill mechanical properties for • low-k ILD compatibility • solder joint fatigue • l
Slide 13: Solder Bump Schematic - Direct Bump on Cu
Solder Bump Schematic - Direct Bump on Cu Ti/NiV/Cu Photoresist Cu Compatible UBM (Ti /NiV /Cu) Device Solder Bump (a) Sputter UBM (b) Apply photoresist, Passivation pattern and develop Final Metal Pad (Cu) Cu (c) Etch UBM (d) Print solder paste 14 0 1 00 Bump on Al : y = 0.0037x + 2.6465 B ump onCu
Slide 14: Black Diamond Flip Chip - Test Vehicle
Black Diamond Flip Chip - Test Vehicle • Test Die – 130nm Node design /processing – 3 Cu in-chip interconnect layers – Black Diamond ILD – 12.3 x 13.5mm die size SnPb – 56 x 62 full array bump w/ 204um pitch – eutectic SnPb solder bump – 80um bump height – 3x20 bump daisy chains at all corners of di
Slide 15: Black Diamond Flip Chip - Bump Quality
Black Diamond Flip Chip - Bump Quality Bump Shear Analysis - cohesive shear mode - no damage at low-k layer Bump Shear Strength Measurement 15 IMAPS Packaging Cu /low-k Workshop San Diego, CA Dec 2003
Slide 16: Black Diamond Flip Chip Package - Substrate & Assembly
Black Diamond Flip Chip Package - Substrate & Assembly • Standard flip chip assembly – Dipping flux – Die placement – Reflow – Underfilling • Underfill DOE with various properties – modulus – CTE – Tg Si Chip • Air-to-air thermal shock (AATS) (TLM C4) – -55°C to 125°C with 60min per cycle • Scanning
Slide 17: Effect of Underfill on Flip Chip Reliability
Effect of Underfill on Flip Chip Reliability Optimized underfill eliminated low K damage through 1000+ Temp Cycle Low Modulus Underfill High Modulus Underfill Cross- Section SEM C-SAM on Flip Chip Post-Underfill post 1000 + Air-to-Air Temp Cycle : no damage (M1-V1-M2 chain under bump) on Cu-low K In
Slide 18: Black Diamond Flip Chip Package - Summary
Black Diamond Flip Chip Package - Summary M1-V1-M2 chain under bump Conclusions • Solder bump compatibility demonstrated using the standard direct-bump-on- Cu process • Underfill selection to be critical for low-k flip chip package integrity • Need complete properties of underfills including Tg, CTE
Slide 19: Cu-Low K Packaging - Summary
Black Diamond Cu-Low K Packaging - Summary Wire Bond Packaging ¾ Bond pad film stack and wire bonding parameters modulate damages to Cu-low K film stack ¾ Successful wire bonding window demonstrated Flip Chip Packaging ¾ Solder bumping to Cu pads compatibility demonstrated ¾ Preliminary flip chi
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