Synopsys, Inc. · NASDAQ:SNPS
Synopsys — Piper Sandler Growth Frontiers Conference 2024
37 slides from Synopsys's conference presentation, Sep 10, 2024
Slide 1: Our Technology, Your Innovation
SYNOPSYS" Our Technology, Your Innovation”
Slide 2: Synopsys Cautionary Statement Regarding Forward Looking Statements
Synopsys Cautionary Statement Regarding Forward Looking Statements This presentation contains certain forward-looking statements within the meaning of the federal securities laws with respect to the proposed transaction between Synopsys and Ansys, including, but not limited to, statements regarding
Slide 3: Ansys Cautionary Statement Regarding Forward-Looking Statements
Ansys Cautionary Statement Regarding Forward-Looking Statements This presentation contains certain “forward-looking statements” within the meaning of the federal securities laws, including Section 27A of the U.S. Securities Act of 1933, as amended, and Section 21E of the Securities Exchange Act of 1
Slide 4: No Offer or Solicitation
No Offer or Solicitation This presentation is for informational purposes only and is not intended to and shall not constitute an offer to buy or sell or the solicitation of an offer to buy or sell any securities, or a solicitation of any vote or approval, nor shall there be any sale of securities in
Slide 5: Unleashing Growth in the Era of Pervasive Intelligence
Unleashing Growth in the Era of Pervasive Intelligence Shankar Krishnamoorthy General Manager, Corporate Staff EDA Group, Synopsys
Slide 6: 37 Years of Advancing Chip Design
37 Years of Advancing Chip Design Synopsys’ Global Presence Leader in software & hardware for chip design CANADA EUROPE ARMENIA S. KOREA US Broadest portfolio of reusable ISRAEL JAPAN CHINA TAIWAN chip design components (IP) INDIA VIETNAM #12 global software CHILE company by revenue $5.96B* ~ 19K* 3
Slide 7: Delivering Outstanding Shareholder Value Creation
Delivering Outstanding Shareholder Value Creation 17% 10% CAGR Revenue ($B) 6% FY20-23 CAGR $5.8 CAGR FY10-20 FY00-10 1986 2000 2010 2020 2023 Strategic Priorities FY20 – FY23 Results • 3nm/2nm leadership across EDA stack • Enabling the multi-die industry transition Technology and • Pioneering AI an
Slide 8: Sharp Acceleration in Semiconductor Demand
Sharp Acceleration in Semiconductor Demand Global Semiconductor Sales1 ($B) Pervasive 8%-10% Intelligence CAGR $1T+ Explosion in IOT & ~6% Cloud CAGR demand for AI chips2 ~4% Mobile CAGR ~$0.5T ~6% COVID Up to Web PC ~18% CAGR Dotcom Bubble Great Recession $400B CAGR in 2027 ~1958 1985 1990 1995 200
Slide 9: Powering the Era of Pervasive Intelligence
Powering the Era of Pervasive Intelligence Artificial intelligence Silicon proliferation Software-defined systems Exponential productivity and efficiency gains More silicon content everywhere New applications, new methodologies Silicon-to-Systems Design Solutions New design paradigms to accelerate i
Slide 10: Creating a Leader in Silicon to Systems Design Solutions
Creating a Leader in Silicon to Systems Design Solutions + Leader in Semiconductor Design Leader in Simulation & Analysis Enhances and Expands TAM to Extends pioneering AI accelerates Silicon to ~$31B, growing at and Cloud leadership Systems strategy ~13% CAGR1 in EDA and simulation 1. Synopsys mana
Slide 11: Pervasive Intelligence Pushing Compute Limits
Pervasive Intelligence Pushing Compute Limits $1B* Training Next-Gen Training FLOPs Scaling in the Context of Moore’s Law Foundation Models 1E+11 Gemini Ultra GPT-4 1E+10 Transformer: 750x / 2 years Claude 2 PaLM (540B) 1E+09 Moore’s Law: 2x / 2 years Megatron-Turing NLG 530B Llama 2-70B GPT-3 Train
Slide 12: Driving Unprecedented Power Consumption
…Driving Unprecedented Power Consumption AI Data Center Power Consumption (GW) nVIDIA H100 GPU 700 Watts* Source: Schneider Electric, December 2023 * Thermal Design Power Energy to train GPT-4 4X 18.7 50 GWh Source: RISE Research Institutes of Sweden, Oct 2023 ChatGPT request vs Google search 4.5 10
Slide 13: Driving Memory and Interface Limits
… Driving Memory and Interface Limits DDR Standards HBM Standards 1800 250 HBM4 MRDIMM v2 1600 Bandwidth (GB/s) 200 1400 HBM3E Bandwidth (GB/s) MRDIMM v1 1200 150 1000 HBM3 800 HBM2E 100 DDR5 5200 600 HBM2E+ DDR5 400 HBM2 HBM2+ 50 DDR4 HBM DDR2 DDR3 200 0 0 2020 2022 2023 2024 2018 2013 2015 2020 20
Slide 14: and Compounded by Talent Shortage
… and Compounded by Talent Shortage 450,000 67,000 400,000 Shortage of Industry demand for Engineers 350,000 114,800 jobs by 2030 300,000 250,000 Design 200,000 150,000 Manufacturing 100,000 2010/2022 2023-2030 Source: Semiconductor Industry Association, 2023 © 2024 Synopsys, Inc. 14
Slide 15: Software Explosion: Cars to Digital Platform
Software Explosion: Cars to Digital Platform Driving Experience Digital Platform Y E S T E R D AY T O D AY Automotive Software Lines of Code Silicon & Software Software as Market per Vehicle Development % of Chip Costs Development 2030 L5 ADAS 5nm ~$84B ~1,000M ~$550M ~2.5x ~10x ~4x ~30-40% 2020 Tod
Slide 16: Process Scaling Gains Lagging Compute Growth Needs
Process Scaling Gains Lagging Compute Growth Needs Grace Hopper GH200 Clearwater Forest Trillion MI300 10+12 Market Needs GAA Technology, Advanced +10 ~ 15% speed Package 10-15% speed at same power N2, 3D Fabric 25-30% power at same speed Angstrom +10 ~ 30% power 5nm 2nm 10-10 7nm Moore’s Law 18A, E
Slide 17: Multiple Innovations Closing the Gap
Multiple Innovations Closing the Gap Trillion Energy Efficiency 10+12 Multi-Die Market Needs AI Compute Domain Acceleration Specific Arch. DTCO, Mfg. Angstrom Innovation 5nm 2nm 10-10 7nm Moore’s Law 10nm * Source: Anand Tech.
Slide 18: Synopsys is Mission Critical to Enabling these Innovations
Synopsys is Mission Critical to Enabling these Innovations Trillion Energy Efficiency 10+12 Multi-Die Market Needs Synopsys AI Compute Domain Acceleration Specific Arch. DTCO, Mfg. Angstrom Innovation 5nm 2nm 10-10 7nm Moore’s Law 10nm * Source: Anand Tech.
Slide 19: Synopsys: Mission Critical for NVIDIA Silicon Success
SYNOPSYS: MISSION CRITICAL FOR NVIDIA SILICON SUCCESS DECADES OF COLLABORATION ACROSS FULL EDA SUITE POWERS ACCELERATED COMPUTING 13X 10X 15X 15X Generative AI Systems Verification Design Simulation Manufacturing Industry’s 1st LLM- Software Computational Based GenAI EDA Testing & Validation of Func
Slide 20: AI-Powered Full-Stack EDA Portfolio
AI-Powered Full-Stack EDA Portfolio Pervasive AI #1 in EDA, 30+ years of EDA investment System Architecture Design Capture Leader in Digital Design and Verification Verification SW, HAV Leader in Hardware-Assisted Verification (HAV) Implementation Signoff Leader in GPU-Accelerated Analog Verificatio
Slide 21: Broadest IP Portfolio with Prominent Positions in Key Blocks
Broadest IP Portfolio with Prominent Positions in Key Blocks 2023 Semi IP Market Other 8% Foundation Broadest IP portfolio, 25 years in the making Basic Peripherals Memory Memory IP15% Processor GPIOs CPU GPU (Uart, I2C) 48% Cluster Cluster Interfaces 29% A decade of sustainable, profitable growth B
Slide 22: We are an AI Company Unlocking Customer Productivity Gains
We are an AI Company Unlocking Customer Productivity Gains
Slide 23: Positioned to Realize Value Creation Potential from AI
Positioned to Realize Value Creation Potential from AI 1 2 3 Surge in AI-Enabled EDA AI-Driven Operational AI Chip Designs Across Full Stack Transformation • 2.5x increase in AI chip • Pioneer since 2020 • Center of Excellence driving design starts since 2018 GenAI roadmap • Expanding industry-leadi
Slide 24: Blistering Pace of AI Innovations
Blistering Pace of AI Innovations Data Analytics (Design.da, Pervasive AI Fab.da, Silicon.da) Synopsys AI Synopsys.ai Opt. Design Space Opt. LLM-Based Initiative (VSO.ai, TSO.ai, (DSO.ai) (GenAI) EDA Launched ASO.ai) DSO.ai DSO.ai DSO.ai DSO.ai DSO.ai 50 100 200 300 400 tapeouts tapeouts tapeouts ta
Slide 25: Synopsys.ai: Pioneering AI-Driven Design Across Full Stack
Synopsys.ai : Pioneering AI-Driven Design Across Full Stack Pervasive AI Generative Collaborative Generative Generate RTL, Test Bench, Expert answers AI Formal Verification Collateral Expert root causes LLM-Based Productivity Boost and Automation DSO.ai VSO.ai TSO.ai ASO.ai 3DSO.ai 10% better 4x TAT
Slide 26: Market Leaders Realizing Significant Gains from Synopsys.ai
Market Leaders Realizing Significant Gains from Synopsys.ai 12% 4nm 25% 20% 28nm Area Lower FinFET Faster Mobile Image sensor CPU Shrink SoC Power TAT DSO.ai* 7nm 3X 4.5% 6.5% Automotive 5nm Fmax 6nm Smaller Productivity HPC Mobile CPU Boost Area VSO.ai* 2X 20% 3.4X HPC Tests Reduction Video IP High
Slide 27: Rapid Adoption of AI-Driven Optimization
Rapid Adoption of AI-Driven Optimization DSO.ai and VSO.ai Design Activity DSO.ai 350 320 300 # of Design Activity 250 200 VSO.ai 187 150 150 100 63 50 50 16 0 2021 2022 2023 2024E
Slide 28: TSO.ai Lowers Cost of Testing a Chip
TSO.ai Lowers Cost of Testing a Chip Exponential Growth in Test Times 56% X Flash Stuck-at Pattern Memory Reduction X X 25% Flash Average Pattern X Memory Reduction X TSO.ai E E ~ 14% E E Mobile/Auto SEQ Test Cycle Source: IEEE Heterogeneous Integration Roadmap 2023 Edition GPUs Reduction Based on R
Slide 29: Accelerating Analog Migration with ASO.ai
Accelerating Analog Migration with ASO.ai Schematic Migration, Circuit Optimization, Layout Migration Current Node Target Node Time intensive Manual Iterative
Slide 30: Accelerating Analog Migration with ASO.ai
Accelerating Analog Migration with ASO.ai Current Node at ion s Fas tC Target Node r on Ite ver Fewer gence ASO.ai Be t t e r Q u a lit y 3X Overall TAT Improvement
Slide 31: Accelerating Analog Migration with ASO.ai
Accelerating Analog Migration with ASO.ai 8X s Fas 7nm Faster Time to it on tC Connectivity IP Optimized Circuit a ter on Fewer I ver 10X gence 22nm Faster migration and mmWave PA RF Optimization ASO.ai Be t t e r Q u ali t y 5X 22nm Faster TTR with Analog IP improved QOR 3X Overall TAT Enabled at L
Slide 32: AI-driven Multi-Die Design Space Optimization with 3DSO.ai
AI-driven Multi-Die Design Space Optimization with 3DSO.ai Industry’s first autonomous exploration and optimization of 2.5D/3DHI design space 10x HBM3 Faster time to best Memory case SI-aware routing 33% HBM3 Improved Eye Memory Diagram @8Gbps 11% UCIe Reduced Transmission Loss 10X Productivity Boos
Slide 33: Synopsys.ai: Pioneering AI-Driven Design Across Full Stack
Synopsys.ai : Pioneering AI-Driven Design Across Full Stack Pervasive AI Generative Collaborative Generative Generate RTL, Test Bench, Expert answers AI Formal Verification Collateral Expert root causes LLM-Based Productivity Boost and Automation Up to 8 hours spent searching for tool usage and opti
Slide 34: LLM-Based EDA (GenAI) is a New Growth Opportunity
LLM-Based EDA (GenAI) is a New Growth Opportunity Knowledge Debug Workflow Collateral Assistant Assistant Assistant Generation Answer expert questions In-context Analysis & Prescriptive Guidance & Design Collateral Gen: RTL, on tools & workflows Design Debug Workflow recommendation Testbench, Assert
Slide 35: Potential AI Impact on Future EDA TAM Growth
Potential AI Impact on Future EDA TAM Growth EDA TAM ~2% of potential incremental EDA TAM growth from AI monetization1 ~12% ~$11B 2023-2028 TAM Growth ~$6B ~12% 2018 2023 Future Source: Management estimates, excludes SIG 1. Assumes AI-enabled EDA is deployed across ~50% of EDA TAM and ~20% of contra
Slide 36: In Closing
In Closing Pervasive Intelligence is projected to accelerate semiconductor demand Synopsys is mission critical in the era of Pervasive Intelligence Synopsys.ai gaining strong traction, delivering consequential results Synopsys leadership in Gen AI opening new growth opportunities
Slide 37: Thank You
SYNOPSYS Our Technology, Your Inn THANK YOU
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