Slide 1: Conquer Complexity with AMD Spartan UltraScale+ FPGAs
Conquer Complexity with AMD Spartan UltraScale+ FPGAs Romisaa Samhoud Product Line Manager | FPGA Cost-Optimized Portfolio October 23, 2024
Slide 2: Agenda
[Public] Agenda 1. AMD Cost-Optimized Portfolio Overview 2. AMD Spartan UltraScale+ FPGA Family 3. Simplify Your Design with Vivado 4. Design Once with Long Lifecycle 5. Application Examples 6. Timelines & Next Steps 2 |
Slide 3: AMD Cost-Optimized Portfolio Applications
[Public] 4K Broadcast 3D Immersive Audio AMD Cost-Optimized Portfolio Applications AI-Enabled ADAS LiDAR Platforms Medical Imaging Robotics Video Collaboration LiDAR Sensor Immersive Video Platform for Video Collaboration 3 |
Slide 4: Broad AMD Portfolio to Address Diverse Needs
[Public] BROAD AMD PORTFOLIO TO ADDRESS DIVERSE NEEDS 45 nm – 28 nm 16 nm Lowest Density Longest Lifecycle, Future-ready Features Integrated Processor ZU4 to ZU19 AMD Zynq 7000 SoC Z-7007S, Z-7012S, Z-7014S, AMD Zynq UltraScale+ SoC Z-7010, Z-7015, Z-7020 ZU1, ZU2, ZU3, ZU3T CG/EG(dual and quad A53)
Slide 5: AMD Spartan UltraScale+ FPGA
AMD Spartan Ultrascale+ FPGA
Slide 6: AMD Spartan UltraScale+ FPGA
[Public] AMD SPARTAN ULTRASCALE+ FPGA High I/O, Low Power & State-of-the-Art Security Features • Industry’s highest I/O to logic cell ratio ≤28nm, enabling cost reduction for I/O-intensive applications • Up to 30% power reduction1 with 16 nm FinFET & power efficiency via hardened DDR and PCIe® • Mos
Slide 7: AMD Spartan UltraScale+ FPGA: Optimized for the Edge
[Public] AMD SPARTAN ULTRASCALE+ FPGA: OPTIMIZED FOR THE EDGE Proven 16 nm Technology Future-Ready Capabilities Flexible I/O Interfaces Low Power • Up to 572 I/Os, 3.3V support • 16 nm FinFET & hard DDR, PCIe® • 3.2G MIPI D-PHY State-of-the-Art Security Block RAM and UltraRAM • Post-Quantum Crypto (
Slide 8: AMD Spartan UltraScale+ FPGA Family Product Table
[Public] AMD SPARTAN ULTRASCALE+ FAMILY PRODUCT TABLE Edge Sensing and Control Board Management Controller I/O Expansion SU150P SU200P SU50P SU55P SU65P SU100P SU10P SU25P SU35P Device SU10P SU25P SU35P SU50P SU55P SU65P SU100P SU150P SU200P LUTs (K) 5 10 16 24 24 30 46 63 100 Logic Cells (K) 11 22
Slide 9: Designed to Facilitate Effective Interfacing
[Public] DESIGNED TO FACILITATE EFFECTIVE INTERFACING Highest I/O to Logic Cell Ratio Increased Connectivity and Flexibility I/O Expansion & Baseboard Management Controller (BMC) Any-to-Any Connectivity for Edge Sensing and Control Motor Motor CPU CPU GPU GPU Camera Sensor Motor Motor Industrial IO
Slide 10: Spartan UltraScale+ FPGA Interfaces Are the Fastest in COP
[Public] AMD SPARTAN ULTRASCALE+ FPGA INTERFACES ARE THE FASTEST IN COP Spartan AMD Spartan 6 Spartan 7 AMD Artix 7 Artix UltraScale+ Feature UltraScale+ FPGA FPGA FPGA FPGA FPGA MIPI (Mbps) 800 800 800 1500 3200 MIPI DPHY Requires external resistor network Native Native DDR4-2400 DDR2-800 DDR3-800
Slide 11: Comprehensive I/O Capabilities
[Public] COMPREHENSIVE I/O CAPABILITIES HDIO HPIO XPIO XP5IO AMD Spartan US+ FPGA x AMD UltraScale+ FPGA x x AMD Versal Adaptive SoC x x Bank Size 42/84 pin 52 pin 54 pin 66 pin Total IO Pin Count 100 – 336 52 - 104 30 – 2064 (SSIT) 0 - 132 Voltages 1.2v – 3.3v 1.2v – 1.8v 0.6v – 1.5v 0.5v – 1.5v Ma
Slide 12: Low Power: 16 nm FinFET and Hardened Interface IP
[Public] LOW POWER: 16 NM FINFET AND HARDENED INTERFACE IP UP TO 30% LOWER TOTAL POWER1 WITH 16 NM FABRIC UP TO 60% LOWER POWER INTERFACING1 Static & Dynamic Power @ 80% Utilization, 200 MHz Total Device Power Normalized to PCIe® and DDR Bandwidth LOWEST DEVICES DENSITY WITH DEVICES HARDENED DDR AND
Slide 13: Advantages for Existing Spartan 6 Customers
[Public] ADVANTAGES FOR EXISTING SPARTAN 6 CUSTOMERS Up to 60% Lower Total Power Up to 2.6X Performance per Watt Static & Dynamic Power @ 80% Utilization, 200 MHz, TJ 85 °C Fmax Per Total Power @ 80% Utilization, 200 MHz , TJ 85 °C 45 nm 16 nm 45 nm 16 nm AMD Spartan 6 AMD Spartan UltraScale+ Sparta
Slide 14: Minimizing Footprint with Advanced Packaging
[Public] MINIMIZING FOOTPRINT WITH ADVANCED PACKAGING Small Form Factor Improved Thermal Dissipation Up to 70% less PCB area Low power and simplified mechanicals Device Chip Scale Package Integrated Fan Out Package Size (mm) 9x9 10x10 12x12 11.5x9.5 9.5x15 9.5x16 AU7P AU10P AU15P SU10P SU25P SU35P Z
Slide 15: Optimizing for Cost by Sizing Down
[Public] OPTIMIZING FOR COST BY SIZING DOWN Cost Reduction for I/O Intensive Applications AMD Spartan 7 Spartan UltraScale+ FPGA Design 7S50 SU10P FPGA Design 210 GPIO 220 GPIO Cost Reduction via Hardened Memory Controllers AMD Artix 7 Spartan UltraScale+ FPGA Design 7A100T SU55P FPGA Design 50K LC
Slide 16: State-of-the-Art Security Features
[Public] STATE-OF-THE-ART SECURITY FEATURES Protect Your IP Prevent Tampering Maximize Uptime • PQC with NIST-approved algorithms • Customizable Tamper Responses • Enhanced SEU performance for • AES-GCM for secure configuration incl. permanent penalty to protect increased reliability the device agai
Slide 17: Maintaining Security Prior to Operation
[Public] MAINTAINING SECURITY PRIOR TO OPERATION AMD 7 Series AMD UltraScale+ AMD Spartan AMD Spartan PASSIVE FEATURES FPGAs and FPGAs and Adaptive 6 FPGA UltraScale+ FPGA Adaptive SoCs SoCs • Confidentiality w/ AES-256 (eFUSE) ✓ ✓ ✓ GCM ✓ GCM • Secure Configuration of PL – RISC V Root of ✓ ✓ ✓ ✓ Tr
Slide 18: Maintaining Security During Operation
[Public] MAINTAINING SECURITY DURING OPERATION AMD AMD 7 Series AMD UltraScale+ AMD Spartan ACTIVE FEATURES Spartan 6 FPGAs and FPGAs and Adaptive UltraScale+ FPGA FPGA Adaptive SoCs SoCs • Single Event Upset (SEU) Checking ✓ ✓ ✓ ✓ • JTAG Disable/Monitor (BSCAN) ✓ ✓ ✓ ✓ • Unique Identifier (Device D
Slide 19: Improved Configuration with AMD Spartan UltraScale+ FPGA
[Public] IMPROVED CONFIGURATION WITH AMD SPARTAN ULTRASCALE+ FPGA AMD Kintex & Virtex Spartan Design AMD Spartan AMD 7 Series UltraScale FPGAs Configuration Mode UltraScale+ Priority 6 FPGAs FPGAs Artix , Kintex, & FPGAs Virtex UltraScale+ FPGAs Slave Serial (x1) Yes Yes Yes Yes Minimum Slave Select
Slide 20: AMD Spartan UltraScale+ FPGA vs. Artix UltraScale+ FPGA
[Public] AMD SPARTAN ULTRASCALE+ FPGA VS. ARTIX ULTRASCALE+ FPGA AMD Artix UltraScale+ FPGA SU150P SU200P SU50P SU55P SU65P SU100P SU10P SU25P SU35P Device SU10P SU25P SU35P SU50P SU55P SU65P SU100P SU150P SU200P Logic Cells (K) 11 22 36 52 52 65 100 137 218 Max. Total I/O 304 304 304 388 352 478
Slide 21: AMD Spartan UltraScale+ FPGA vs. Artix UltraScale+ FPGA
[Public] AMD SPARTAN ULTRASCALE+ FPGA VS. ARTIX ULTRASCALE+ FPGA Overlapping Logic Density 60-80K LC 100K LC 150K LC 200K LC SU65P SU100P SU150P SU200P Hard Memory Controller LPDDR4x/5 Security Upgrades 1x PCIe® Gen4x4 2x PCIe® Gen4x4 or 1x Gen4x8 Lower Densities 3.2G MIPI Higher 3.3V to Logic Cell
Slide 22: Leadership in Tools with AMD Vivado Design Tools
[Public] LEADERSHIP IN TOOLS WITH AMD VIVADO Design TOOLS 22 |
Slide 23: Accelerate TTM with Proven Vivado Design Tools
[Public] ACCELERATE TTM WITH PROVEN VIVADO DESIGN TOOLS Industry Challenges Learning Curve Developer Efficiency Trusted Results AMD Approach • Single tool supporting entire portfolio1 • Single tool for the entire design cycle • Proven performance over PVT • >100 Soft IPs in catalog • Fast design ite
Slide 24: One Tool: Less Complexity from Simulation to Debug
[Public] ONE TOOL: LESS COMPLEXITY FROM SIMULATION TO DEBUG STATUS QUO - FRAGMENTED FLOW AMD APPROACH - UNIFIED FLOW Third Party 2 FPGA Vendor Synthesis Place & Route Single tool for end-to- Third Party 1 end design Simulation Optimization Synthesis Debug Dedicated single- Simulation Place & Route s
Slide 25: Trusted COP FPGA Provider with Proven Product Lifecycles
[Public] TRUSTED COP FPGA PROVIDER WITH PROVEN PRODUCT LIFECYCLES 25 |
Slide 26: Long-Term Investment in Cost-Optimized Portfolio
[Public] LONG-TERM INVESTMENT IN COST-OPTIMIZED PORTFOLIO 2010 2020 Today 2030 2035 2040+ 2045+ Extended Standard Lifecycle Lifecycle Worldwide sales from AMD and authorized Standard Lifecycle Extended Lifecycle distributors Standard Lifecycle Extended Lifecycle Standard Lifecycle Extended Lifecycle
Slide 27: Application Examples
APPLICATION EXAMPLES
Slide 28: AMD Spartan UltraScale+ FPGA Application Examples
[Public] AMD SPARTAN ULTRASCALE+ FPGA APPLICATION EXAMPLES Industrial Medical Comms Factory Automation, Robotics Smart Patient Monitor 4G and 5G Wireless Infrastructure IIoT Gateways & Edge Appliances Ultrasound, CT/MRI Scan Board Controller Smart City, Smart Grid Multi-Stream Endosc
Slide 29: Versatile Data Acquisition and Edge Processing
[Public] VERSATILE DATA ACQUISITION AND EDGE PROCESSING Digital IO PCIe/ Ethernet interface to host ADCs Timing control Data Acquisition Application Requirements Spartan UltraScale+ FPGA Capabilities • Parallelization and independent real-time • PL Architecture with up to 572 flexible I/Os supportin
Slide 30: Machine Vision and Video Capture Cards
[Public] MACHINE VISION AND VIDEO CAPTURE CARDS MIPI Hard 10GigE or Hard Compliant x86 Camera DPHY Memory Memory PCIe® Controller CoaXpress Controller or LVDS LPDDR4x/5 2.0 LPDDR4x/5 Gen4 Host Pair or USB LPDDR4x/5 LPDDR4x/5 Camera Module Frame Grabber Machine Vision Application Requirements Spartan
Slide 31: Data Center Server I/O and Board Management Controller
[Public] DATA CENTER SERVER I/O AND BOARD MANAGEMENT CONTROLLER CPU CPU GPU GPU Cooling Memory I/O Expansion Configurations Power control BMC Application Requirements Spartan UltraScale+ FPGA Capabilities • Space constrained and low power requirement • FPGA can provide power management solutions and
Slide 32: Getting Started and Next Steps
GETTING STARTED AND NEXT STEPS
Slide 33: Getting Started Milestones and Available Assets
[Public] GETTING STARTED MILESTONES AND AVAILABLE ASSETS Product Launch (March’24) Early Access Program (NOW) Production (Mid’25) • Adaptive Computing Blog • Overview Datasheet • Silicon Production Shipping • Infographic & Listicle • Architecture Manuals • Tools Production Support • COP Portfolio eB
Slide 34: Start Working on Power Delivery Solutions
[Public] START WORKING ON POWER DELIVERY SOLUTIONS Strategic Power Partnerships • Power reference designs to springboard your solution • Design for low cost, low BOM & high channel integration • High frequency switching regulators to reduce inductor size • Single PMIC solutions • Telemetry enabled p
Slide 35: Start Prototyping with UltraScale+ Boards Today
[Public] START PROTOTYPING WITH ULTASCALE+ BOARDS TODAY Avnet AUBoard 15P Development Kit Avnet ZUBoard 1CG MPSoC Development Kit Featuring the AMD Artix UltraScale+ AU15P device Featuring the AMD Zynq UltraScale+ ZU1CG device Feature List Feature List • Targets XCAU15P-2FFVB676E device • Targets XC
Slide 36: Next Steps
[Public] NEXT STEPS • Visit the AMD Spartan UltraScale+ FPGA webpage: https://www.amd.com/spartan-ultrascale-plus.html Check the AMD Webpages for More • Learn how AMD stacks on top of the competition: Information https://www.amd.com/en/products/adaptive-socs-and-fpgas/cost- optimized-portfolio/scale
Slide 37: AMD Spartan UltraScale+ FPGA
[Public] AMD SPARTAN ULTRASCALE+ FPGA High I/O, Low Power & State-of-the-Art Security Features • Industry’s highest I/O to logic cell ratio ≤28nm, enabling cost reduction for I/O-intensive applications • Up to 30% power reduction1 with 16 nm FinFET & power efficiency via hardened DDR and PCIe® • Mos
Slide 38: AMDe
Sf AMDe
Slide 39: Endnotes
[Public] ENDNOTES 1 Based on AMD internal analysis December 2023, comparing the total I/O to logic cell ratios in the AMD product data sheets for AMD Spartan UltraScale+ FPGAs to previous generations of AMD Cost-Optimized FPGAs. (SUS-01) Based on AMD internal analysis in December 2023, using the pro
Slide 40: Endnotes
[Public] ENDNOTES 7 AMD Spartan UltraScale+ FPGA SU200P FPGA memory controller bandwidth based on the data sheet against 28 nm AMD Artix 7 7A200T FPGA. (SUS-07) 8 Spartan UltraScale+ FPGA SU200P PCIe® bandwidth based on the data sheet against 28nm Artix 7 7A200T FPGA. (SUS-08) 9 Based on data sheet
Slide 41: Disclaimer and Attributions
[Public] DISCLAIMER AND ATTRIBUTIONS DISCLAIMER Artix, Kria, Kintex, Microscale, Spartan, UltraScale, Versal, Vitis, Virtex, Vivado, Zynq, 41 |
Slide 42: Appendix: Product Table
Appendix: Product Table
Slide 43: AMD Spartan UltraScale+ FPGA Product Table
AMD Spartan UltraScale+ FPGA Product Table Device Name SU10P SU25P SU35P SU50P SU55P SU65P SU100P SU150P SU200P System Logic Cells (K) 11 22 36 52 52 65 100 137 218 Logic CLB Flip-Flops (K) 10 20 32 48 48 60 92 126 200 CLB LUTs (K) 5 10 16 24 24 30 46 63 100 Max. Distributed RAM (Mb) 0.07 0.14 0.23