Slide 1: OCTEON TX2 Infrastructure Processor Family
OCTEON TX2 Infrastructure Processor Family
Slide 2: Announcement of Next Generation Infrastructure Processors
Announcement of Next Generation Infrastructure Processors OCTEON® TX2 OCTEON Fusion® © 2020 Marvell confidential. All rights reserved. 2
Slide 3: OCTEON TX2 Announcement
OCTEON TX2 Announcement Industry-leading data path performance up to 200Gbps for networking and security applications Up to 5 100G MACs integrated in the OCTEON TX2 infrastructure processor leading to significant TCO advantage OCTEON TX2 Infrastructure Processor family combines 4 to 36 Armv8-
Slide 4: OCTEON TX2 Announcement
OCTEON TX2 Announcement Target Markets: ‒ Enterprise Networking / security ‒ 5G wireless infrastructure ‒ Service provider / multi-access Edge compute ‒ Cloud / Data Center Highest Performance Infrastructure Processor Family © 2020 Marvell confidential. All rights reserved. 4
Slide 5: A Long History of Compute Innovation
A Long History of Compute Innovation OCTEON Fusion Micro/ Multicore Macro Cell OCTEON® OCTEON ThunderX Control Arm Multi-Core Fusion® ThunderX ® processors Embedded Dataplane Micro/Macro Arm Server OCTEON for Storage Processors Offload Cell Processors Processors EPS Security Fusion 5G 1995 1998 2001
Slide 6: Announcement of Next Generation Infrastructure Processors
Announcement of Next Generation Infrastructure Processors This is the standard bullet slide Keep bullet points brief Use line spacing to clearly separate each point ‒ Second line of text example © 2020 Marvell confidential. All rights reserved. 6
Slide 7: New Horizons – New Solutions
New Horizons – New Solutions DATA INFRASTRUCTURE X86 / GPU Arm >150B devices shipped* *ARM August 2019 Financial Results SPECIALIZED COMPUTE © 2020 Marvell confidential. All rights reserved. 7
Slide 8: From the Core to the Edge – Technology Leadership
From the Core to the Edge – Technology Leadership DATA CENTER CARRIER ENTERPRISE EDGE THINGS End-to-end SECURITY Packet Processing Compute Signal Processing © 2020 Marvell confidential. All rights reserved. 8
Slide 9: What is a Marvell Infrastructure Processor?
What is a Marvell Infrastructure Processor? Specialized compute, Packet Processing Interconnected Marvell’s heritage CPU cores Encryption I N T E R C O N N E C T Highly programmable Optimized Arm cores Regular Expression & configurable blocks with Marvell interconnect intelligently connected Flexibl
Slide 10: Infrastructure Processor: Leading Compute and Data Plane
Infrastructure Processor: Leading Compute and Data Plane High-end firewall Routers and switches Macro / micro BTS Crypto offload Control / data, crypto offload Transport layer and crypto CN9130 SMB firewall / Security gateway Control plane processor CN96xx CN98xx CN92xx CN96xx CN9130 CN92xx CN96xx ©
Slide 11: Marvell Infrastructure Processor Timeline
Marvell Infrastructure Processor Timeline 240 Gbps Data Throughput Performance 200Gbps Security IPsec Gen1 Gen2 Gen3 Gen4 Gen5 © 2020 Marvell confidential. All rights reserved. 11
Slide 12: OCTEON TX2 Infrastructure Processor: CN98/96xx
OCTEON TX2 Infrastructure Processor: CN98/96xx CN913X CN92XX CN96XX CN98XX 4C A72 12-18C ARMv8.2 18-24C ARMv8.2 24-36C ARMv8.2 20 Gbps 50 Gbps 100 Gbps 200 Gbps NOW NOW NOW Q2’2020 Unified software development environment supporting standard Linux, DPDK, containers & virtualization © 2020 Marvell co
Slide 13: OCTEON TX2 Infrastructure Processor: CN98/96xx
OCTEON TX2 Infrastructure Processor: CN98/96xx Introducing the industry’s highest performing Infrastructure Processor family Power Regular Sec Vault TrustZone Management Expression • Highest Compute Engine (SPECINTRate) SOC in its Compress/ SIMD SIMD Switch & vNIC Decomp AES AES FPU FPU PCIe v4 Syst
Slide 14: CN9130 – Best Performance/Watt Processor Targeting SOHO/SMB
CN9130 – Best Performance/Watt Processor Targeting SOHO/SMB CN9130 block diagram Cortex-A72 Cortex-A72 Cortex-A72 Cortex-A72 • CN913X – Up to 4 cores (20 Gbps) Armv8 CPU Armv8 CPU Armv8 CPU Armv8 CPU L1 L1 L1 L1 L1 L1 L1 L1 DDR4 64-bit + ECC • Supports up to 18 SERDES lanes D-cache I-cache D-cache I
Slide 15: OCTEON TX/TX2: Portfolio
OCTEON TX/TX2: Portfolio Metric CN913X CN83XX CN92XX CN96XX CN98XX Cores 4 8-24 12-18 18-24 30-36 Max Freq 2.2G 2.0G 2.0G 2.4G 2.4G Cache (MLC, LLC) 2MB 8MB 5MB, 8MB 5MB, 14MB 8MB, 21MB DDR4 1@2400MTS 2@2100MTS 2@3200MTS 3@3200MTS 6@3200MTS Up to 3 Ethernet 12x10G 4x25G, 8x10G 3 x100G/12x25G 5 x100G
Slide 16: Unified Software Development Environment
Unified Software Development Environment VPP Arm V8 ENGINE Crypto ISA Standard Linux Apps IPSEC Hyperscan L2/L3 Secure TCP/IP Storage Linux Kernel Routing/Bridging/iptables IPSEC Boot Loader Secure Boot U-Boot/UEFI © 2020 Marvell confidential. All rights reserved. 16
Slide 17: Marvell Security Acceleration Performance Advantage
Marvell Security Acceleration Performance Advantage Infrastructure Processor with Crypto accelerator Performance vs. software implementation with QAT AES-CBC Performance based on DPDK Cryptolib Crypto Marvell Requirement Intel Xeon Infrastructure (1KB Packet) Processor 50G *128W 50W 100G **155W 75W
Slide 18: Proof Point: Security Appliance Example
Proof Point: Security Appliance Example Intrusion Protection │ Firewall │ IPSEC 32 Core x86 Marvell CN98XX NIC NIC 8x25G 4x10/40G Higher Performance Intrusion Prevention 12G 50G Firewall 50G 200G IPSEC 6G 100G © 2020 Marvell confidential. All rights reserved. 18
Slide 19: Proof Point: Network Visibility and Analysis Appliance
Proof Point: Network Visibility and Analysis Appliance Infrastructure CPU with FPGA Processor Xeon – 2187NT Marvell FPGA CN96XX: 24 Core Ethernet Ethernet Power: 235W Power: <75W Price: 3X+ Price: 1X © 2020 Marvell confidential. All rights reserved. 19
Slide 20: Proof Point: 5G Macro Base Station
Proof Point: 5G Macro Base Station DDR4 memory DDR4 memory 1 to 3 DDR4 channels DDR4 memory 10/25GbE OCTEON Fusion RF CNF95XX RF OCTEON Fusion OCTEON TX2 10/25G/40GbE CNF95XX CN96XX Backhaul OCTEON Fusion RF CNF95XX OCTEON TX2 Arm V8.2 SoC 5G gNodeB design © 2020 Marvell confidential. All rights res
Slide 21: Summary
Summary • Industry-leading data path performance up to 200Gbps for networking and security applications • Up to 5 100G MACs integrated in the OCTEON TX2 infrastructure processor leading to significant TCO advantage • OCTEON TX2 Infrastructure Processor family scales 4 to 36 Arm v8-based architecture
Slide 22: Traditional Data Infrastructure Compute Options
Traditional Data Infrastructure Compute Options CPU only FPGA Custom ASIC Arm Fixed Arm Arm / X86 ASIC Compute LUT and Gates Interconnect DEVELOPMENT SPEED 5 DEVELOPMENT SPEED 3 DEVELOPMENT SPEED 1 POWER 2 POWER 2 POWER 5 PERFORMANCE 2 PERFORMANCE 3 PERFORMANCE 5 PROGRAMMABILITY 5 PROGRAMMABILITY 5
Slide 23: OCTEON TX2 Value Proposition: The Best of Both Worlds
OCTEON TX2 Value Proposition: The Best of Both Worlds 3 I/O bridges (each 1+Tbps) for 200Gbps of Data-plane processing I/O Bridge I/O Bridge I/O Bridge DDR DDR DDR DDR DDR DDR Cluster Cluster Cluster Cluster Cluster Cluster CN98xx architecture © 2020 Marvell confidential. All rights reserved. 23
Slide 24: Marvell – Essential technology, done right
ia MARVELL Essential technology, done right™