Synopsys, Inc. · NASDAQ:SNPS
Synopsys — Investor Presentation (December 2014)
51 slides from Synopsys's investor presentation, December 2014
Slide 1: Corporate Overview for Investors
Corporate Overview for Investors December 2014 © Synopsys 2014 1
Slide 2: Forward-Looking Statements
Forward-Looking Statements This presentation contains forward-looking statements under the safe harbor provisions of Section 21E of the Securities Exchange Act of 1934, including statements regarding projected financial results and long-term growth rates. For a discussion of important factors that c
Slide 3: Synopsys Introduction
Synopsys Introduction • Global leader in Electronic Design Automation (EDA), the tools and technologies used to design chips • Leading provider of semiconductor Intellectual Property (IP), the reusable building blocks that are used for chip designs • The market & technology leader: Virtually all lea
Slide 4: Synopsys Snapshot
Synopsys Snapshot FY14 FY15 (Target*) Revenue: $2.057B $2.185 – $2.225B NG EPS: $2.53 $2.67 – $2.72 Business Model: ~90% time-based Revenue Sources: ~½ International Employees: ~9,440 Market Cap: ~$6.7B Founded: 1986 Patents Granted: ~2,299 * These targets were provided by Synopsys as of December 3,
Slide 5: Synopsys: The Market & Technology Leader
Synopsys: The Market & Technology Leader Uniquely Positioned for Stability and Growth • Dynamic markets • Clear technology leadership • Financial strength and growth © Synopsys 2014 5
Slide 6: Global Value Chain
Global Value Chain EDA & IP – At the Heart of Accelerating Electronics Innovation EDA & IP* $9.0B Embedded Software* $2.8B** Foundry $41.2B Semiconductors $348B Electronic Systems $1,488B *Estimates are provided for EDA/IP/Embedded Software ** 2013 value Source: IC Insights, VDC Research, Synopsys E
Slide 7: Helping Design the Chips Inside
Helping Design the Chips Inside Impacting Everyone, Everything, Everywhere, Every Day Mobile Computing & Peripherals Medical Data Center & Networking Automotive Military / Aerospace Cloud Infrastructure Digital Home Internet of Things Industrial © Synopsys 2014 7
Slide 8: Mobile
Mobile Global Internet Device Sales 3,000,000,000 2,500,000,000 2,000,000,000 We Are Here 1,500,000,000 1,000,000,000 Smartphones 500,000,000 Personal Computers 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013E 2014E 2015E 2016E Personal Computers Smartphones Tablets Source: Bus
Slide 9: Data, Data, Data – Cloud Infrastructure
Data, Data, Data – Cloud Infrastructure Smartphone PC Tablet Data Access Smart TV By 2017, the annual global IP traffic will surpass the zettabyte threshold (1.4 zettabytes). Source: Cisco Systems, VNI Global Mobile Data Traffic Forecast Update 2013 © Synopsys 2014 9
Slide 10: Internet of Things
Internet of Things Power Buildings Cars Toasters Lamps…? Software SW & E/E Lines of % Vehicle Code Cost Sensors Example 1970 100K <9% “Smart” Microprocessors Storage 1990 1M 33% Communication 2010 100M >40% © Synopsys 2014 10
Slide 11: Significant Growth in Sensors
Sensors Are Everywhere Significant Growth in Sensors Sensor Units to Grow to 30 Billion Units in 2017 Consumer 30B Units 30000 Automotive Computing 25000 Smartphones Feature Phones 20000 Industrial Other Communications 15000 10B Units 10000 5000 0 2009 2010 2011 2012 2013 2014 2015 2016 2017 Source:
Slide 12: Semiconductor Design Complexity
Semiconductor Design Complexity • An advanced design today will take 18-24 months to complete, and can cost up to $200M • Design starts (total) have declined slightly over the past several years, but the complexity of those designs has increased exponentially, requiring more, and more advanced, EDA
Slide 13: Complexity Drives Demand for Tools
Complexity Drives Demand for Tools Synopsys Consistently Leads in Advanced Designs Leader at Leader at Leader at Leader at 45/40nm 32/28nm 22/20nm 14/16nm • Leading companies migrating to very advanced nodes; some waiting at 32/28nm • Many choosing to skip 22/20nm and go to 16/14nm FinFET • Ramp of
Slide 14: Designs Are Becoming More Costly
Designs Are Becoming More Costly Primary Designs $350 $300 Note: Primary Designs are new and more-complex design(s), typically shipping in high-volumes, are developed on the next process node, require qualification on a whole new range of IP, and typically contain extensive software content $250 Cos
Slide 15: First to 16/14nm Design
First to 16/14nm Design Synopsys Solutions Used in Every FinFET Design Samsung and Synopsys Collaborate to Achieve First 14-nanometer FinFET Tapeout (Dec, 2012) GLOBALFOUNDRIES and Synopsys Partner To Provide Comprehensive Design Environment for Foundry’s 14nm-XM FinFET offering (December 20, 2012)
Slide 16: Comprehensive FinFET Solution
Comprehensive FinFET Solution “Clearly, from a technical point of view, Moore’s Law is alive Synopsys’ FinFET and well, and Synopsys is central in driving it forward,” Aart Leadership de Geus, Synopsys Chairman and Co-CEO • Have invested in the extremely fast-growing FinFET segment for almost a deca
Slide 17: Blue Chip Customer Base
Blue Chip Customer Base • Customer base consists of virtually all semiconductor companies in the world, including all of the top 20 • One ~10% customer (Q414 & FY14) • For many years we have collaborated closely with market leaders, including top foundries, IDMs and fabless customers © Synopsys 2014
Slide 18: Synopsys: The Market & Technology Leader
Synopsys: The Market & Technology Leader Uniquely Positioned for Stability and Growth • Dynamic markets • Clear technology leadership • Financial strength and growth © Synopsys 2014 18
Slide 19: Broadest Portfolio of Best-in-Class Technology
Broadest Portfolio of Best-in-Class Technology Systems System Design Verification IP Implementation SoC Manufacturing Silicon © Synopsys 2014 19
Slide 20: #1 in Core EDA
#1 in Core EDA • 62% of current revenue; 4% trailing twelve- month revenue growth* System Design • ~90% of 20nm and below tape-outs have used Synopsys implementation Verification IP Implementation • Vast majority of advanced designs utilize Synopsys digital verification • Manufacturing 19 of the top
Slide 21: Introducing IC Compiler II
Introducing IC Compiler II Game-Changer in Place & Route Rebuild Rethink Reuse New Infrastructure New Engines Best of IC Compiler I Data Model Multi Multi Hier Mode Timer Floor Plan Linear Placer Multi Multi Thread Voltage Multi Opt. Clock Tree Zroute View Enabling 10X Throughput © Synopsys 2014 21
Slide 22: Early Customer Successes
Early Customer Successes A B 10X Faster Placement Opt. 25M Instances in Under 4 hrs 4X Faster Clock Opt. 10X TAT in Design Planning Tapeout Underway Tapeout Underway C D 8X Faster Placement Opt. 6X Faster Placement Opt. 2X Faster Clock Opt. 3X Smaller Memory Tapeout Underway Tapeout Underway © Synop
Slide 23: Introducing Verification Continuum
Introducing Industry’s #1 Verification Continuum • Game-changing Planning & Coverage new platform launched in 2014 Debug #1 • Seamless integration • Built around best- #1 #1 #1 in-class engines; Virtual Static & FPGA adding unified Simulation Emulation Prototype Formal Prototype debug, compile • Goa
Slide 24: 2014: Verification Compiler
2014: Verification Compiler Comprehensive, Best-in-Class Verification in One Product © Synopsys 2014 24
Slide 25: Verification Compiler
Verification Compiler Next Gen Native Complete Technology Integrations Access Compilers GUIs Low Power Formal Unified Dbases APIs CDC Adv. Lint Flows Enable “3X” Verification Productivity © Synopsys 2014 25
Slide 26: Introducing ZeBu Server-3
Introducing ZeBu Server-3 Industry’s Fastest Emulation System Debug Comprehensive debug Performance with full signal visibility Speeds HW/SW bring-up and Verdi3 integration and SoC verification up to 4X for faster time-to-market \ Architecture Advanced architecture for Hybrid Emulation lower total c
Slide 27: #1 in Manufacturing
#1 in Manufacturing • 9% of current revenue; -2.5% trailing twelve-month revenue growth* System Design • Mask data prep tools used by 8 of the top 10 semiconductor manufacturers Verification IP Implementation • TCAD tools used by 9 of the top 10 semiconductor manufacturers • Manufacturing Yield mana
Slide 28: Growth in Core EDA + Manufacturing
Growth in Core EDA + Manufacturing Estimated Long-Term Organic Growth Rate • Generally in the low-to-mid single digit range* • Growth drivers: ‒Segment growth + market share gains Segment Growth Drivers • Semi R&D growth • Demand for new designs, new devices • Increasing complexity requiring new, ad
Slide 29: Growth in IP/Software Solutions
Growth in IP/Software Solutions • 26% of current revenue; 12% trailing twelve- month revenue growth* System Design • Estimated long-term organic revenue growth: generally in the low double-digits** Verification IP Implementation • Top-20 semiconductor vendors continue to outsource more IP to Synopsy
Slide 30: #2 IP Vendor
#2 IP Vendor Leader in Interface, Analog & Memory IP Leadership Enables Investment in Quality, Support, Features and Processes Design IP Revenue, Worldwide (in Millions)* Design IP Revenue, Wired Interface 2013 Rank Company 2013 Share 1 Synopsys 193.3 43.5% 2 Silicon Im age 49.1 11.0% 3 Cadence 44.8
Slide 31: Third-Party IP – Synopsys Differentiator
Third-Party IP – Synopsys Differentiator Specialty I/O Application Application Graphic CPU CPU RAM RAM ROM Core(s) LVDS, Etc Established Provider 15+ years of investment and Flash Flash Storage execution RAM RAM RAM RAM Interface Resource On-Chip Bus DDR DDR memory Commitment Interface (UARTs/Timers
Slide 32: 3rd Party IP Usage Will Continue to Double Through 2017
3rd Party IP Usage Will Continue to Double Through 2017 Consumer Increasing Wireless Design Communication Complexity Escalating Design Costs 2017 Data Processing 2012 Shorter Time Window for Overall 3rd New Product Automotive party design IP Launch use in 2012 Industrial Overall 3rd party design IP
Slide 33: IP Market Growing to $3.5B by 2017
IP Market Growing to $3.5B by 2017 4,000.00 25.00% 3,511.00 3,500.00 3,179.00 3,000.00 2,885.00 20.00% 2,608.00 2,456.70 2,500.00 2,203.00 15.00% 2,000.00 1,925.90 1,695.00 1,500.00 10.00% 1,000.00 5.00% 500.00 0.00 0.00% 2010 2011 2012 2013 2014 2015 2016 2017 IP Revenue ($M) IP Growth (%) Source:
Slide 34: IP Business Models
IP Business Models Single Use Multi-Use Agreement Engineering Service • Customer buys IP for • Customer buys a pool • Customer pays for a specific project of IP that can be used porting IP to specific over a multi-year semiconductor • Revenue recognized period until the pool is process or up front e
Slide 35: IP Accelerated Initiative
IP Accelerated Initiative Fast Prototyping, Software Development & Integration Redefining the IP Supplier Paradigm IP Accelerated IP Accelerated augments broad, Broad IP silicon-proven DesignWare IP Portfolio portfolio with: DesignWare IP Development Kits • IP prototyping kits with reference designs
Slide 36: System-Level Design
System-Level Design • #1 provider of system design solutions HW/SW Transactions including tools, models and services for: ‒Accelerating software development ‒Hardware/Software integration Register Transfer ‒System validation • Immense chip/system complexity requires new approaches to HW/SW and syste
Slide 37: Synopsys Expands TAM w/ Coverity
Synopsys Expands TAM w/ Coverity • Acquired Coverity for $375M ($334M net of cash acquired) Synopsys Enters Software Quality and Security Market with Coverity Acquisition • Leading provider of Software Coverity Improves Code Quality and Security, Resulting in Better Quality, Testing and Security Sof
Slide 38: $500M Market Today, Growing ~20%
$500M Market Today, Growing ~20% Synopsys Is Now the Market Leader Software Quality Software tools to observe, measure, and evaluate software complexity, Analysis and Measurement size, productivity and risk. $1,000 Market 906 $900 785 Market Share $800 $700 678 Coverity, 585 Troux, Others, 13.0% $60
Slide 39: Current Synopsys Customers Plus Brand New Customer Base
Current Synopsys Customers Plus Brand New Customer Base Current Semis/Systems Customers New Verticals, Customers Banking, Financial Services, Energy, Different Users, Different Budgets Aerospace/Defense, Software, Internet, Industrial, etc. System Design Naturally adjacent Core competencies: • Algor
Slide 40: Synopsys: The Market & Technology Leader
Synopsys: The Market & Technology Leader Uniquely Positioned for Stability and Growth • Dynamic markets • Clear technology leadership • Financial strength and growth © Synopsys 2014 40
Slide 41: Growth and Predictability
Growth and Predictability Revenue ($M) $2,500 $2,205 $1,962 $2,057 $2,000 $1,756 $1,536 $1,500 • Predictable, time-based $1,000 revenue model $500 $0 • Entered FY15 with ~80% of FY11 FY12 FY13 FY14 FY15 Guide-Mid* revenue in hand NG EPS • Non-cancellable backlog: $3.5B $3.00 $2.70 3-yr backlog end o
Slide 42: Predictable Time-Based Revenue
Predictable Time-Based Revenue 3-Year Backlog • Significant Non-cancellable $3,500 $3.5B 3-year Backlog $3,000 $2,500 $3.1B – $3.5B at end of FY14 $2.7B $2,000 – More backlog than next 2 largest $1,500 EDA players combined $1,000 $500 • Predictable, time-based $0 FY12 FY13 FY14 revenue model – In Q4
Slide 43: Strong Operating Cash Flow
Strong Operating Cash Flow Annual Operating Cash Flow • Roughly tracks EBITDA less $600 $551 cash taxes over time $486 $497 At least $500 $450 • OCF is lumpy $400 ‒ Difficult to forecast period to period $ Millions $300 ‒ Timing of large contracts $200 ‒ Disbursements (affected by M&A) $100 • Goal i
Slide 44: Efficient Resource Management
Efficient Resource Management 100% 90% 20% 23% • Most profitable ($) in EDA 80% 7% 70% 6% • Have reduced G&A and S&M spending (as % of revenue) 60% 27% 21% 50% • Expect to maintain NG R&D 40% spend at ~30% of revenue 33% 30% 29% • Goal is to focus on global 20% operational efficiency to 10% 17% 17%
Slide 45: Technologically & Geographically Diversified
Technologically & Geographically Diversified 3% 3% 3% 100% 100% 90% 10% 9% 9% 90% 21% 23% 25% 80% 80% 25% 25% 26% 70% 70% 17% 14% 12% $ Millions $ Millions 60% 60% 13% 14% 13% 50% 50% 40% 40% 30% 62% 63% 62% 30% 49% 50% 51% 20% 20% 10% 10% 0% 0% FY12 FY13 FY14 FY12 FY13 FY14 Core EDA IP & SW Solutio
Slide 46: Capital Allocation Strategy
Capital Allocation Strategy Disciplined resource management and allocation Actively explore TAM-expanding R&D and M&A opportunities Optimize the use of our strong cash flow, through a balance of M&A, debt reduction and stock buybacks © Synopsys 2014 46
Slide 47: Solid Balance Sheet
Solid Balance Sheet US Non US • $911M net cash at end of $1,004 $1,022 $986 Q414 $1,000 • Split of U.S. vs. non-U.S. $800 cash can influence $700 investment decisions $ Millions $600 • Buybacks and debt repayments funded entirely $400 with U.S. cash $200 • Typically like to hold a minimum of ~$100M
Slide 48: Returning Cash to Shareholders
Returning Cash to Shareholders Annual Share Buybacks • Over the last 5 years, spent $500 $925M on buybacks $435 $400 o Purchased 3.1M SNPS shares for $120M in FY14 $ Millions $300 • $380M remaining on our $200 current share repurchase $145 $120 authorization* $100 $40 • Goal is to optimize the use o
Slide 49: Long-term Operating Model
Long-term Operating Model* Primary long-term objective is to drive high-single-digit EPS growth through a mix of the following elements: • Organically grow traditional EDA revenue generally in the low-to-mid single digit range • Organically grow IP and Software Solutions revenue generally in the low
Slide 50: Summary
Summary • Dynamic markets – World’s leading EDA supplier and #2 IP vendor • Clear technology leadership – Broadest portfolio of best-in-class technology • Financial strength and growth – Excellent financial position and execution © Synopsys 2014 50
Slide 51: Thank You
Thank You SyNOPsys" ccelerating Innovation