Synopsys, Inc. · NASDAQ:SNPS
Synopsys — Investor Day (March 2024)
182 slides from Synopsys's investor day presentation, Mar 20, 2024
Slide 1: Exhibit 99.1
Exhibit 99.1 © 2024 Synopsys, Inc. 1
Slide 2: Synopsys Cautionary Statement Regarding Forward Looking Statements
Synopsys Cautionary Statement Regarding Forward Looking Statements This presentation contains certain forward-looking statements within the meaning of the federal securities laws with respect to the proposed transaction between Synopsys and Ansys, including, but not limited to, statements regarding
Slide 3: Ansys Cautionary Statement Regarding Forward-Looking Statements
Ansys Cautionary Statement Regarding Forward-Looking Statements This presentation contains certain “forward-looking statements” within the meaning of the federal securities laws, including Section 27A of the U.S. Securities Act of 1933, as amended, and Section 21E of the Securities Exchange Act of 1
Slide 4: No Offer or Solicitation
No Offer or Solicitation This presentation is for informational purposes only and is not intended to and shall not constitute an offer to buy or sell or the solicitation of an offer to buy or sell any securities, or a solicitation of any vote or approval, nor shall there be any sale of securities in
Slide 5: Welcome Synopsys Investor Day 2024
Welcome Synopsys Investor Day 2024 Trey Campbell SVP, Investor Relations
Slide 6: Our Technology, Your Innovation
SyNOPsys' Our Technology, Your Innovation”
Slide 7: Today's Agenda
Today's Agenda Sassine Ghazi Seizing Unprecedented Opportunity President and CEO Unleashing Growth in EDA with Pioneering Innovations Shankar Krishnamoorthy GM and Corp Staff, EDA Group Accelerating Systems Strategy Ravi Subramanian Ph.D., General Manager, Systems Design Group Synopsys Design IP Joh
Slide 8: Our Technology, Your Innovation
SyNOPsys' Our Technology, Your Innovation”
Slide 9: Seizing Unprecedented Opportunity
Seizing Unprecedented Opportunity Synopsys Investor Day 2024 Sassine Ghazi President and Chief Executive Officer
Slide 10: Proven Track Record of Powering Innovation and Resilient, Industry-Leading Growth
Proven Track Record of Powering Innovation and Resilient, Industry-Leading Growth
Slide 11: Empowering Customers to Ignite Tomorrow's Technology
Empowering Customers to Ignite Tomorrow's Technology VALUE PURPOSE MISSION PROPOSITION To power innovation today Empower We maximize customers’ that ignites the ingenuity technology innovators R&D capabilities and of tomorrow everywhere multiply their productivity © 2024 Synopsys, Inc.
Slide 12: 37-Year History of Pioneering New Businesses
37-Year History of Pioneering New Businesses to Deliver Sustained Long-Term Growth 17% CAGR 10% FY20-23 6% CAGR $5.8 CAGR FY10-20 FY00-10 1986 2000 2010 2020 2023 Acquisition Formed 1 Systems SLM of SDG 2 Software Security SIG Quality Started Foundation & IP IP business Processors Pioneered Verifica
Slide 13: Leading Global Software and Semiconductor Company
Leading Global Software and Semiconductor Company Public Companies Synopsys has a Rare Combination of 1 Criteria Scale, Growth and Profitability SEMICONDUCTOR SOFTWARE $5B+ LTM Revenue ~10%+ NTM Growth 35%+ CY24 Non-GAAP Operating Margin 1. Based on ~220 public software companies and ~200 public sem
Slide 14: A High-Quality Business Portfolio
A High-Quality Business Portfolio FY23 Revenue Design Automation Design IP SIG Total in Application in IP in EDA #1 #2 #1 Software Testing Revenue CAGR 17% 21% 15% 18% (FY21–FY23) Operating Margin 1 1 1 2 38.1% 34.5% 14.5% 35.1% (FY23) Note: Figures based on Synopsys FY results in its 10-K as filed
Slide 15: Delivering Outstanding Shareholder Value Creation
Delivering Outstanding Shareholder Value Creation 2 Strategic Priorities FY20 – FY23 Results 3-Year TSR Performance • 3nm/2nm leadership across EDA stack 140% • Enabling the multi-die industry transition Technology and • Pioneering AI and Cloud in EDA Innovation Leadership 3 • Next-gen IP across all
Slide 16: Unprecedented Market Opportunity Driven by Structural Trends
Unprecedented Market Opportunity Driven by Structural Trends
Slide 17: The era of Pervasive Intelligence
The era of PERVASIVE INTELLIGENCE Artificial Silicon Software-Defined Intelligence Proliferation Systems Exponential productivity More silicon content New applications, and efficiency gains everywhere new methodologies But pushing the energy But productivity and But increased complexity, and compute
Slide 18: Sharp Acceleration in Semiconductor Demand
Sharp Acceleration in Semiconductor Demand 1 Global Semiconductor Sales ($B) Pervasive ~10% $1T+ Intelligence CAGR Explosion in ~6% IOT & demand for CAGR Cloud 2 AI chips ~4% Mobile CAGR ~$0.5T Up to COVID ~6% Web CAGR Great Recession $400B ~18% Dotcom PC Bubble CAGR in 2027 ~1958 1985 1990 1995 200
Slide 19: Advanced Chip Requirements Face Multiple Constraints
Advanced Chip Requirements Face Multiple Constraints Exponentially Increasing Demands… …Are Constrained by Technology and Costs Increasing Slowing Compute of Classic Memory & Data Center Edge Moore’s Performance Semis “Laws” I/O ‘Walls’ Law Improved Skyrocketing Energy Costs Chip Power Global Chip C
Slide 20: New Design Paradigm Needed to Meet Compute Demand
New Design Paradigm Needed to Meet Compute Demand 3 New Paradigm: Silicon lifecycle 2 SILICON to optimization Silicon/ from design SYSTEMS Hardware/ to in-field 1 DESIGN Software Co-Design Multi-Die MOORE’S LAW 2020 1960 © 2024 Synopsys, Inc. Power, Performance & Area (PPA) Metrics
Slide 21: Silicon to Systems Design Creates New Challenges
Silicon to Systems Design Creates New Challenges PPA Performance, Power, Area Tightening Timelines Customer Design Exploding Complexity Objectives Resource Time to Utilization Results Optimizing across all three vectors © 2024 Synopsys, Inc.
Slide 22: EDA & IP Innovation Essential to Move the Industry Forward
EDA & IP Innovation Essential to Move the Industry Forward …to Address Customer Needs Key Elements of Modern Advanced Chip Design… Deeply Integrated State-of-the-art ✓ PPA Toolchain Performance, ‘Shift Left’ Massive • AI-powered Power, Area Architectural Verification • ‘Chip-up’ Multi-die Design Exp
Slide 23: EDA and IP Growth Outpacing Semiconductor R&D
EDA and IP Growth Outpacing Semiconductor R&D 1 IP TAM EDA TAM Semi R&D Semi Sales CAGR 2018-23 Pervasive Intelligence 300 accelerating growth IP Growth consistently ~14% above EDA TAM 250 Growth consistently New silicon entrants EDA ~12% above Semi R&D TAM 200 Resilient growth: Semi Steady growth s
Slide 24: Continued Momentum from TAM Drivers to Propel Growth
Continued Momentum from TAM Drivers to Propel Growth 2023 TAM TAM CAGR Historical Outlook 2018 - 2023 2023 - 2028E ~$18B ~13% ~13% • Increased design activity – AI/HPC, Automotive • Faster tech cycles ~$7B IP ~14% ~15% • Multi-die • Accelerated outsourcing • R&D growth linked to accelerated semi sal
Slide 25: Well-Positioned to Win
SYNOPSYS” = TAN = ae Well-Positioned to Win
Slide 26: Our Strategy for Sustained, Value-Creating Growth
Our Strategy for Sustained, Value-Creating Growth Strategic Priorities Strategy From Silicon … … to Systems Technology and Innovation Leadership Lead innovation in EDA and IP for Expand into new adjacent growth the era of Pervasive Intelligence areas in software-defined systems Industry-Leading Grow
Slide 27: Industry-Leading, Full-Stack EDA Solution
Industry-Leading, Full-Stack EDA Solution Industry Pervasive AI Leader #1 in EDA, 30+ years of EDA investment System Architecture ✓ 65% of Synopsys FY23 revenue Design Capture ✓ Verification ✓ Leader in digital design and verification Implementation ✓ Leader in GPU-accelerated analog verification Si
Slide 28: Broadest IP Portfolio with Prominent Positions in Key Blocks
Broadest IP Portfolio with Prominent Positions in Key Blocks 2023 Semi IP Market Other 8% Foundation Broadest IP portfolio, 25 years in the making IP15% Processor CPU GPU 48% Cluster Cluster Interfaces 29% A decade of sustainable, profitable growth Bus Fabrics Leader in Interfaces and Foundation IP
Slide 29: Over-Indexed to Fastest Growing Segments in the Industry
Over-Indexed to Fastest Growing Segments in the Industry EDA IP BUSINESS MIX TAM CAGR TAM CAGR BUSINESS MIX (FY23, Total = 100%) FY20-23 FY20-23 (FY23, Total = 100%) Digital Design Interface & ~15% ~18% & Verification Foundation IP Custom Design, Processor ~14% ~12% Manuf. & PCB & Other IP TAM TAM ©
Slide 30: We are an AI Company
We are an AI Company...Unlocking Massive Customer Productivity Gains…
Slide 31: ...in the Early Stages of the AI Transition
...in the Early Stages of the AI Transition
Slide 32: Positioned to Realize Value Creation Potential from AI
Positioned to Realize Value Creation Potential from AI 1 2 3 Surge in AI AI- -E Enabled nabled E EDA DA AI-Driven Operational AI Chip Designs Acro Across ss Full Full St Stac ack k Transformation • 2.5x increase in AI chip • Pioneer since 2020 • Center of Excellence driving design starts since 2018
Slide 33: Industry-Leading AI Suite with Expanding Capabilities
2024E+ Continued Expansion Industry-Leading AI Suite with Expanding Capabilities Pervasive AI 2023 Generative AI onwards System Architecture Synopsys.ai LLM-Based EDA Design Capture November 2023 Verification 2022 Data Analytics onwards Implementation Synopsys.ai Signoff (with Design.da, Fab.da, Sil
Slide 34: Strong Adoption Momentum in Our Earliest Offering (DSO.ai)
Strong Adoption Momentum in Our Earliest Offering (DSO.ai) Increasing customer adoption of DSO.ai… …with significant opportunity to further penetrate Select Customers: 2 35 ~20% ~10-15% 20 In production in ~20% of Utilized in ~10-15% 3 4 addressable customer base of design content 11 4 5 uplift vs b
Slide 35: AI-Enabled EDA Delivers Step-Change Improvements
AI-Enabled EDA Delivers Step-Change Improvements AI-driven solutions to optimize silicon performance, improve power efficiency and accelerate design throughout the entire EDA flow DIGITAL DESIGN VERIFICATION TEST ANALOG DESIGN Better quality Faster and Lowers cost of Migration of designs with less b
Slide 36: Potential AI Impact on Future EDA TAM Growth
Potential AI Impact on Future EDA TAM Growth EDA TAM ~2% of potential incremental EDA TAM 1 growth from AI monetization ~12% ~$11B 2023-2028 TAM Growth ~12% ~$6B 2018 2023 Future Source: Management estimates, excludes SIG 1. Assumes AI-enabled EDA is deployed across ~50% of EDA TAM and ~20% of contr
Slide 37: Creating the Leader in Silicon to Systems Design Solutions
Creating the Leader in Silicon to Systems Design Solutions
Slide 38: Silicon to Systems Transition Ongoing Across Verticals
Systems to Silicon Silicon to Systems Transition Ongoing Across Verticals SYSTEMS SPECTRUM Electronics Electro-Mechanical Semiconductor Companies Systems Companies “Classic” Advanced Industrial Chips Computing High-Tech Automotive Aerospace Equipment Others MECHANICAL MECHANICAL MECHANICAL MECHANICA
Slide 39: Most Comprehensive System Virtualization Solution Portfolio
Most Comprehensive System Virtualization Solution Portfolio Product Operating Virtual model of product in environment in Environment 1 Virtual Product Virtual model of product Building the Most Comprehensive Digital Twin Software development & Software in Electronics test automation INDUSTRY LEADER
Slide 40: Attractive, Industry-Leading ~$31B TAM
1 Attractive, Industry-Leading ~$31B TAM Estimated TAM CAGR 1 2023 TAM 2023-2028E Underlying Secular 2 R&D Growth Trends ~$31B ~13% • Sustainability Systems ~$10B • Autonomy ~10% ~1.5x Simulation • IoT & Analysis • Engineering Digital Transformation ~6-7% • Model-Based Systems Engineering Systems So
Slide 41: Accelerating Our Silicon to Systems Strategy
Accelerating Our Silicon to Systems Strategy From Silicon … … to Systems Strengthens Accelerates expansion capabilities in into new growth advanced chip design verticals 31% 22% technology Semiconductor / Aerospace • Opportunities to improve High-Tech EDA penetration • Extends portfolio with • Scale
Slide 42: What Our Customers Have to Say About the Combination
What Our Customers Have to Say About the Combination In a multi-die environment, power and Chips are now complex systems requiring ““ thermal analysis needs to happen not only harmonization of power integrity, sophisticated at the individual die level, but also at the structure, and thermal and elec
Slide 43: What Our Customers Have to Say About the Combination
What Our Customers Have to Say About the Combination ““ Multi-die systems provide a way Bringing Synopsys and Ansys forward to achieve reduced power and together holds the promise of a area and higher performance, powerful digital twin solution that can opening the door to a new era of expedite and
Slide 44: Ansys
Ansys Synopsys Investor Day 2024 Ajei Gopal President and Chief Executive Officer, Ansys
Slide 45: Creating a Leader in Silicon to Systems Design Solutions
Creating a Leader in Silicon to Systems Design Solutions + Leader in Semiconductor Design Leader in Simulation & Analysis Enhances and Expands TAM to Extends pioneering AI accelerates Silicon to ~$31B, growing at and Cloud leadership 1 Systems strategy ~13% CAGR in EDA and simulation 1. Synopsys man
Slide 46: Committed to Industry-Leading Revenue Growth and Margin Accretion
Committed to Industry-Leading Revenue Growth and Margin Accretion
Slide 47: Long-Term Financial Objectives Aligned with Strategy
1 Long-Term Financial Objectives Aligned with Strategy Non-GAAP Op. Revenue Free Cash Flow Non-GAAP EPS Margin 17% 28% 35% 23% 26% 26% FY20-23 FY20-23 Non-GAAP FY20-23 FCF FY20-23 Non-GAAP 2 3 2 CAGR Op. Margin Margin EPS CAGR Combined company long-term, multi-year objectives Industry-leading Long-t
Slide 48: Seizing Unprecedented Opportunity
Seizing Unprecedented Opportunity Multi-decade track record of delivering outsized shareholder value Solving customer challenges in the face of exploding complexity Technology leadership in AI, multi-die & Silicon to Systems design Commitment to resilient, market-leading growth © 2024 Synopsys, Inc.
Slide 49: Thank You
SYNOPSYS” Our Technology, Your Inn THANK YOU
Slide 50: Our Technology, Your Innovation
SyNOPsys' Our Technology, Your Innovation”
Slide 51: Unleashing Growth in EDA with Pioneering Innovations
Unleashing Growth in EDA with Pioneering Innovations Shankar Krishnamoorthy GM and Corp Staff, EDA Group
Slide 52: Synopsys EDA is Moving from Important to Mission Critical
Synopsys EDA is Moving from Important to Mission Critical
Slide 53: Process Scaling Gains Lagging Compute Growth Needs
Process Scaling Gains Lagging Compute Growth Needs Grace Hopper GH200 Clearwater Forest Trillion +12 10 MI300 Market Needs GAA Technology, Advanced Package 10-15% speed at same po N2 w , e 3D r Fabric Angstrom 25-30% power at same speed +10 ~ 15% speed +10 ~ 30% power -10 10 2nm 5nm Moore’s Law 7nm
Slide 54: Multiple Innovations Closing the Gap
Multiple Innovations Closing the Gap Trillion +12 Energy 10 Efficiency Multi-Die Market Needs AI Compute Domain Acceleration Specific Arch. Angstrom DTCO, Mfg. Innovation -10 10 2nm 5nm Moore’s Law 7nm 10nm © 2024 Synopsys, Inc. * Source: Anand Tech.
Slide 55: Synopsys is Mission Critical to Enabling these Innovations
Synopsys is Mission Critical to Enabling these Innovations Trillion +12 Energy 10 Efficiency Multi-Die Market Needs Synopsys AI Compute EDA Domain Acceleration Specific Arch. Angstrom DTCO, Mfg. Innovation -10 10 2nm 5nm Moore’s Law 7nm 10nm © 2024 Synopsys, Inc. * Source: Anand Tech.
Slide 56: Synopsys EDA Well Positioned with Breadth and Depth of Portfolio
Synopsys EDA Well Positioned with Breadth and Depth of Portfolio
Slide 57: AI-Powered Full-Stack EDA Portfolio
AI-Powered Full-Stack EDA Portfolio Pervasive AI #1 in EDA, 30+ years of EDA investment System Architecture 65% of Synopsys FY23 revenue Design Capture Verification Leader in Digital Design and Verification Implementation Leader in GPU-Accelerated Analog Verification Signoff Test & SLM Gold Standard
Slide 58: Industry-Leading EDA Products
Industry-Leading EDA Products System Architecture TCAD, OPC, Smart Mfg. Design Capture Test & SLM Implementation Verification Signoff Proteus Platform Architect OPC TestMAX Design DFT/ATPG Sentaurus 3DIC Compiler® Compiler TCAD PrimeTime® TSO.ai VCS® Fusion Fab.da 3DSO.ai StarRC Compiler PVT VSO.ai
Slide 59: Preferred Choice for Established and Emerging Nodes
Preferred Choice for Established and Emerging Nodes Synopsys Usage Industry Tapeouts at ≤7nm for the Tapeouts at ≤7nm 500 400 P&R Signoff Synthesis Active Designs 300 Taped Out Designs 200 Digital Analog 100 Verification Verification 0 Source: Synopsys Global Technical Services, February 2024 © 2024
Slide 60: Pioneering Innovations Enable Semiconductor Progress
Pioneering Innovations Enable Semiconductor Progress RTL Exploration and Synopsys.ai Optimization (with VSO.ai, TSO.ai) March 2020 March 2023 AI-Driven Fusion GPU Acceleration GPU Acceleration Synopsys.ai Optimization 3DSO.ai Architecture SPICE OPC LLM-Based EDA (DSO.ai) SNUG 2024 Nov 2018 April 202
Slide 61: Delivering Strong Double-Digit Growth
Delivering Strong Double-Digit Growth Design Automation Revenue 17% CAGR: FY21-FY23 Low single-digit CAGR Energy Efficiency Multi-Die Synopsys AI Compute EDA Domain Acceleration Specific Architecture DTCO Mfg. Innovation FY17 FY18 FY19 FY20 FY21 FY22 FY23 FY24E © 2024 Synopsys, Inc. Revenue, $M
Slide 62: It's All About the Architecture
It’s All About the Architecture
Slide 63: Synopsys Next-Gen Fusion EDA Architecture
Synopsys Next-Gen Fusion EDA Architecture Separate Tools with Value Links Synthesis P&R Extraction Timing Pre 2016 © 2024 Synopsys, Inc.
Slide 64: Electronics to Physics Fusion
Electronics to Physics Fusion Angstrom Era on the Horizon Synopsys Next-Gen Fusion EDA Architecture Superior PPA, Separate Tools Fusion API Architecture Convergence for Angstrom Era with Value Links For Hyperconvergence Rapid integration of New Functions EMIR ECO Formal Stress Synthesis Timing Verif
Slide 65: Pioneering Innovations Unleash New Growth Vectors: March to Angstroms
Pioneering Innovations Unleash New Growth Vectors March to Angstroms
Slide 66: Process Geometry Shrinking to Angstrom Levels
Process Geometry Shrinking to Angstrom Levels >28nm 22nm 16/14nm 10nm 7nm 5nm 3nm 2nm/18A 14A <10A 2011 2013 2015 2017 2019 2021 2024E 2026E* 2028E* © 2024 Synopsys, Inc.
Slide 67: Maximizing Process Entitlement in Angstrom Era
Maximizing Process Entitlement in Angstrom Era PPA Optimized Double Patterning Nanosheet Optimized Pre-PDK DTCO Library Double Patterning Hybrid Row Backside Power Backside Clock, Signal P&R SI Modeling Hierarchical Modeling Variability Modeling Hybrid Extraction Signoff Model Based OPC Inverse Lith
Slide 68: Maximizing Process Entitlement in Angstrom Era
Maximizing Process Entitlement in Angstrom Era Ultra Short Lib DPT PPA Optimized Pre-PDK DTCO Nanosheet Opt M1 Routing Opt. Libraries Foundation Libraries Library Backside Power Backside Power Double Patterning Hybrid Row Distribution Distribution Fusion Compiler P&R SMC, 3DIC HyperGrid SI STA Hyper
Slide 69: Maximizing Process Entitlement in Angstrom Era
Maximizing Process Entitlement in Angstrom Era TSMC and Synopsys help our mutual customers Synopsys provides designers with access to achieve the best-in-class design results across industry-leading certified EDA flows and IP that the full Synopsys EDA stack on TSMC's most deliver the best performan
Slide 70: Pioneering Innovations Unleash New Growth Vectors: Synopsys.ai
Pioneering Innovations Unleash New Growth Vectors Synopsys.ai
Slide 71: EDA Workflow Offers Opportunities for AI
EDA Workflow Offers Opportunities for AI Architecture Verification Test & SLM Implementation Signoff Manufacturing © 2024 Synopsys, Inc.
Slide 72: EDA Workflow Offers Opportunities for AI
EDA Workflow Offers Opportunities for AI Architectural Specification Verification Design Spec Test Plan Design Under Test Tests Improve Regression Debug Coverage System Failures Coverage Debug Cycle Cycle Pass Fail Results © 2024 Synopsys, Inc.
Slide 73: EDA Workflow Offers Opportunities for AI
EDA Workflow Offers Opportunities for AI Hyperconvergent Flow Tool Options Cell Libraries RTL Design Floorplans Metal Stacks Implementation EDA RTL Synthesis Design Planning Place & Route Signoff ECO Closure © 2024 Synopsys, Inc. Fusion Compiler
Slide 74: EDA Workflow Offers Opportunities for AI
EDA Workflow Offers Opportunities for AI Tool Options Cell Libraries RTL Design Floorplans Metal Stacks Implementation RTL Synthesis Design Planning Place & Route ECO Closure © 2024 Synopsys, Inc. Fusion Compiler
Slide 75: Blistering Pace of AI Innovations
Blistering Pace of AI Innovations Data Analytics (Design.da, Pervasive AI Fab.da, Silicon.da) Synopsys AI Synopsys.ai Opt. Design Space Opt. LLM-Based Initiative (VSO.ai, TSO.ai, (DSO.ai) (GenAI) EDA Launched ASO.ai) DSO.ai DSO.ai DSO.ai DSO.ai DSO.ai 300 50 100 200 400 tapeouts tapeouts tapeouts ta
Slide 76: Market Leaders Realizing Significant Gains from Synopsys.ai
Market Leaders Realizing Significant Gains from Synopsys.ai 12% 25% 20% 4nm FinFET 28nm Area Lower Faster Mobile Image sensor CPU Shrink SoC Power TAT DSO.ai* 4.5% 6.5% 3X 7nm Fmax Smaller 5nm 6nm Automotive Productivity HPC Mobile Boost Area CPU 15% 2X 2X VSO.ai* Automotive Coverage Tests Faster HP
Slide 77: Rapid Adoption of AI-Driven Optimization
Rapid Adoption of AI-Driven Optimization DSO.ai DSO.ai and VSO.ai Design Activity 350 320 300 250 VSO.ai 200 187 150 150 100 63 50 50 16 0 2022 2023 2024E 2021 © 2024 Synopsys, Inc. # of Design Activity
Slide 78: Accelerating Analog Migration with ASO.ai
Accelerating Analog Migration with ASO.ai Schematic Migration, Circuit Optimization, Layout Migration Current Node Target Node Time intensive Manual Iterative © 2024 Synopsys, Inc.
Slide 79: Accelerating Analog Migration with ASO.ai
e c n e g r e v n o C t B s e a t F t e r Accelerating Analog Migration with ASO.ai Current Node Target Node ASO.ai 3X Overall TAT Improvement © 2024 Synopsys, Inc. Q u a s l i n t o y i t a r e t I r e w e F
Slide 80: Accelerating Analog Migration with ASO.ai
e c n e g r e v n o C t B s e a t F t e r Accelerating Analog Migration with ASO.ai ASO.ai Faster Time to Results 10X Faster TAT Analog Circuit Optimization 3X Faster TAT ASO.ai Analog IP Node Migration Enabled at Leading Foundries 3X Overall TAT Improvement © 2024 Synopsys, Inc. Q u a s l n i t o y
Slide 81: TSO.ai Lowers Cost of Testing a Chip
TSO.ai Lowers Cost of Testing a Chip Customer Results Exponential Growth in Test Times (Pattern Count Reduction) X 45% - 70% X Mobile X X X TSO.ai 18% - 60% Systems E E E E Source: IEEE Heterogeneous Integration Roadmap 2023 Edition 19% - 25% Graphics Die test time directly proportional to test patt
Slide 82: LLM-Based EDA (GenAI) is a New Growth Opportunity
LLM-Based EDA (GenAI) is a New Growth Opportunity Collateral Knowledge Debug Workflow Assistant Assistant Assistant Generation Answer expert questions Prescriptive Guidance & In-context Analysis & Design Collateral Gen: RTL, on tools & workflows Design Debug Workflow recommendation Testbench, Assert
Slide 83: Pioneering Innovations Unleash New Growth Vectors: Multi-Die
Pioneering Innovations Unleash New Growth Vectors Multi-Die
Slide 84: Multi-Die Packages: Enabling Many Transformative Products
Multi-Die Packages: Enabling Many Transformative Products AMD NVIDIA Google Intel Instinct MI300 Grace Hopper TPU v5 Clearwater Forest (Xeon) Gen AI Accelerator Gen AI Superchip “Hypercomputer” AI Nextgen Server Chip 304 GPUs, 192GB HBM3 72-core CPU, H100 Tensor GPU, 256 chips/pod, 95GB HBM2e 288-co
Slide 85: Estimated 30% of EDA SW TAM Driven by Multi-Die by 2027
Estimated 30% of EDA SW TAM Driven by Multi-Die by 2027 EDA SW TAM Estimate for 1 2 Multi-die Migration Forecast Digital Implementation and Signoff 2D Designs By 2027 2.5D / 3D Designs Server/AI ~90% ~70% PC/Client Consumer ~10% systems ~10% Automotive FY22 FY23 FY24E FY25E FY26E FY27E 1. Source: Yo
Slide 86: Chip-Up Disruption to Meet Trillion-Scale Multi-Die Challenge
Chip-Up Disruption to Meet Trillion-Scale Multi-Die Challenge Co-Optimize Die/Package Explore, Design, Analyze System Together in one environment Chip-Up Disruption 2D/3D-stacked Chiplets (10s of dies,100Bx Transistors) HBM Design & Integration Automation (Bandwidth/Latency Optimization) Multi-scale
Slide 87: Comprehensive Multi-Die Package Solution
Comprehensive Multi-Die Package Solution Synopsys AI-Powered architecture exploration and design 3DIC Compiler Platform with software co-development and validation Broadest Die-to-Die IP portfolio on silicon-proven technologies Industry’s only unified and scalable platform for 3D heterogeneous integ
Slide 88: Enabling Multi-Die Innovation at Market Makers
Enabling Multi-Die Innovation at Market Makers CPU HPC / AI Hyperscale Company Semi Company System Company o Delivered A architecture Made over 10 different Optimized thermal profiles to intricacy with 3D integration pieces of silicon to behave unlock significant energy for 300B+ transistor system a
Slide 89: New Innovations to Accelerate Multi-Die Exploration/Design
New Innovations to Accelerate Multi-Die Exploration/Design Fast Native Thermal Analysis 3DSO.ai: AI-Driven Optimization Hours vs. Days 10x Productivity Boost in Incremental Analysis Superior QoR © 2024 Synopsys, Inc.
Slide 90: Pioneering Innovations Unleash New Growth Vectors: Energy Efficiency
Pioneering Innovations Unleash New Growth Vectors Energy Efficiency
Slide 91: AI Driving Unprecedented Power Consumption
AI Driving Unprecedented Power Consumption nVIDIA H100 GPU AI Data Center Power Consumption (GW) 700 Watts* Source: Schneider Electric, December 2023 * Thermal Design Power Energy to train GPT-4 4X 50 GWh 18.7 Increase Source: RISE Research Institutes of Sweden, Oct 2023 ChatGPT request vs Google se
Slide 92: Optimizing Power at Every Design Phase
Optimizing Power at Every Design Phase System Architecture Design Capture Implementation Signoff Test & SLM Software Profiling HW-SW Arch. HW Micro Arch. PPA Chip Power Adaptive Voltage Tradeoffs Optimization Optimization Analysis Scaling ZeBu Empower, PrimePower RTL Fusion Compiler PrimePower SLM P
Slide 93: Pioneering Innovations Unleash New Growth Vectors: EDA Compute Acceleration
Pioneering Innovations Unleash New Growth Vectors EDA Compute Acceleration
Slide 94: EDA Compute Acceleration Innovations
EDA Compute Acceleration Innovations Multi Core Distributed Rapid Transition to 96, Distributed Computing 128 Cores with 100s of Machines 10X TAT for Timing Near-Linear Acceleration Signoff on 64 Cores of Formal Verification Synopsys EDA Cloud GPU Elastic, Scalable Acceleration of Computing on Cloud
Slide 95: Synopsys: Mission Critical for NVIDIA Silicon Success
SYNOPSYS: MISSION CRITICAL FOR NVIDIA SILICON SUCCESS DECADES OF COLLABORATION ACROSS FULL EDA SUITE POWERS ACCELERATED COMPUTING 13X 10X 15X 15X Systems Generative AI st Industry’s 1 LLM- Manufacturing Software Verification Design Simulation Based GenAI EDA Computational Testing & Validation of SPI
Slide 96: Synopsys EDA is Mission Critical in the Era of Pervasive AI
Synopsys EDA is Mission Critical in the Era of Pervasive AI Well Positioned with Breadth and Depth of Portfolio Next-Gen Architecture to Rapidly Fuse Electronics & Multi-Physics Pioneering in Emerging Areas Unleashes New Growth Vectors © 2024 Synopsys, Inc.
Slide 97: Thank You
SYNOPSYS” Our Technology, Your Inn THANK YOU
Slide 98: Our Technology, Your Innovation
SyNOPsys' Our Technology, Your Innovation”
Slide 99: Accelerating Systems Strategy
Accelerating Systems Strategy Synopsys Investor Day 2024 Ravi Subramanian, Ph.D. General Manager, Systems Design Group
Slide 100: Pervasive Intelligence Driven By Increasing Silicon and Software Content
Pervasive Intelligence Driven By Increasing Silicon and Software Content In Systems Products Autonomy and Systems companies Driving demand for massive software-defined systems re-architecting products, compute, both at the edge reshaping industries business models and and the data center development
Slide 101: Silicon to Systems Transition Ongoing Across Verticals
Systems to Silicon Silicon to Systems Transition Ongoing Across Verticals SYSTEMS SPECTRUM Electronics Electro-Mechanical Semiconductor Companies Systems Companies “Classic” Advanced Industrial Chips Computing High-Tech Automotive Aerospace Equipment Others MECHANICAL MECHANICAL MECHANICAL MECHANICA
Slide 102: Systems R&D Processes Are More Complex, More Costly
Systems R&D Processes Are More Complex, More Costly YESTERDAY TODAY 1 % of electronics in the cost of a new car … …increasing by ~2.5x Increasing cost of 18% 45% electronics 2000 2030 Sequential design flows… …are now continuous Hardware Product Silicon Hardware Software Test in-field New Test Silic
Slide 103: Massive Challenges Facing Auto Industry Forcing Change
Massive Challenges Facing Auto Industry Forcing Change… Driving Experience Digital Platform Y E S T E R D AY T O D AY Automotive Software Lines of Code Silicon & Software Software as Market per Vehicle Development % of Chip Costs Development 2030 L5 ADAS 5nm ~$84B ~1,000M ~$550M ~30-40% ~2.5x ~10x ~
Slide 104: Previous Product Testing Methods Are Unsustainable
…and Previous Product Testing Methods Are Unsustainable… Physical Safety Control 1B+ Miles Autonomy Testing Levels Validation of Driving Autonomous vehicles would have to be driven hundreds of “ Millions of miles and sometimes hundreds of billions of miles to demonstrate their reliability… …existing
Slide 105: Solving These Challenges Requires Digital Twin Technologies
Solving These Challenges Requires Digital Twin Technologies Digital Twin A virtual representation of a physical product 1 Expected Customer Benefits Increase revenue Accelerate Improve product Increase contribution growth time to market quality margin +10% +50% +25% ~5-10% Source: Digital twins: The
Slide 106: Industry Leaders Agree Virtualization Is Necessary Today
Industry Leaders Agree Virtualization Is Necessary Today Virtual “ development is essential for solving our challenges. ” Volkswagen Synopsys 2022 Virtual Prototyping Day © 2024 Synopsys, Inc.
Slide 107: Our Silicon to Systems Solutions Journey to Digital Twin
Our Silicon to Systems Solutions Journey to Digital Twin… Product Operating Virtual model of product in environment in Environment 1 Virtual Product Virtual model of product Building the Most Comprehensive Digital Twin Software development & Software in Electronics test automation INDUSTRY LEADER TM
Slide 108: Paving the Way for an Electronics Digital Twin (eDT)
…Paving the Way for an Electronics Digital Twin (eDT)… Digital Twin Fabric Enabling multi-fidelity, multi-domain, multi-level digital twins Products Silicon Silicon Chips in Electronics Architecture of Software in Lifecycle Chip Management Chip Electronics in Product Electronics Virtual Model Softwa
Slide 109: Including Silicon Lifecycle Management Innovation
…Including Silicon Lifecycle Management Innovation Monitoring and optimization of relevant chip metrics across lifecycle stages Margin Yield Silicon Predictive Optimization Optimization Insights Maintenance & in-field Optimization In-Chip In-Ramp In-Production In-Field In-Design Monitors Design Anal
Slide 110: Synopsys Uniquely Positioned to Address Challenge
Synopsys Uniquely Positioned to Address Challenge 9 of Top 10 Auto OEMs use Synopsys virtualization technology Engineers focused on digital twin technologies serving 400+ all automotive geographies Virtual chip models from top automotive semis and OEMs 65 ~$3B Systems Software + SLM TAM FY20-23 Syst
Slide 111: Acquisition of Ansys Accelerates Our eDT Strategy
1 Acquisition of Ansys Accelerates Our eDT Strategy Embedded Software Multi-physics Driving Scenarios Embedded Software Multi-physics Hardware-in-the- Tools for Safety and Domains Vehicle Dynamics Generators Tools for Safety and Domains Vehicle Dynamics Loop (HIL) Systems Security Sensors and Covera
Slide 112: Pending Combination Will Accelerate Automotive Opportunity
Pending Combination Will Accelerate Automotive Opportunity New Joint Solutions Automotive Digital Twin • Core multi-physics (mechanical, • Virtual vehicle for electronic systems thermal, etc.) and software testing • Comprehensive digital twins for SDV • Auto-specific virtual testing (e.g., • Softwar
Slide 113: Systems to Silicon: Opportunities Across Other Verticals
Systems to Silicon “…As Well As Opportunities Across Other Verticals” SYSTEMS SPECTRUM Electronics Electro-Mechanical Semiconductor Companies Systems Companies “Classic” Advanced Industrial Chips Computing High-Tech Automotive Aerospace Equipment Others MECHANICAL MECHANICAL MECHANICAL MECHANICAL ME
Slide 114: Accelerates Expansion via Focused Go-to-Market
…and Accelerates Expansion via Focused Go-to-Market From Silicon … … to Systems Strengthens Accelerates expansion capabilities in into new growth advanced chip design verticals 31% 22% technology Semiconductor / Aerospace High-Tech • Opportunities to improve • Extends portfolio with EDA Penetration
Slide 115: Unlocking ~$13 Billion Systems TAM with Ansys
Unlocking ~$13 Billion Systems TAM with Ansys Potential Simulation additional Systems TAM & Analysis future TAM from digital twin ~$10B ~$13B Systems Software & SLM ~$3B Combined Systems TAM TAM CAGR >20% ~10% ~12% (2023–2028) Note: Figures exclude impact from SIG © 2024 Synopsys, Inc. Source: Synop
Slide 116: In Summary
In Summary Unprecedented opportunity as silicon, software, and systems meet Industry leader in hardware assisted verification and virtualization Strategically positioned to win with proof points in automotive Ansys acquisition will accelerate our Silicon to Systems strategy © 2024 Synopsys, Inc.
Slide 117: Thank You
SYNOPSYS” Our Technology, Your Inn THANK YOU
Slide 118: Our Technology, Your Innovation
SyNOPsys' Our Technology, Your Innovation”
Slide 119: Synopsys Design IP
Synopsys Design IP John Koeter Senior VP, Product Management and Strategy
Slide 120: Major Components of Semiconductor Chip
Major Components of Semiconductor Chip CPU GPU Cluster Cluster Bus Fabrics AI Sensors Accelerator Memory (NPU) Embedded Processors Security System Interfaces Peripheral Interfaces IP (PCIe, Ethernet…) (USB, HDMI…) * Small boxes are standard cell library elements © 2024 Synopsys, Inc. Memory Basic Pe
Slide 121: 3rd Party Design IP Market: $7.05B in 2023
3rd Party Design IP Market: $7.05B in 2023 Other 8% CPU CPU GP GPU U Cl Clu uste ster r Cl Clu uste ster r Foundation IP 15% B Bu us s Fa Fab bri rics cs Processor IP 48% AI AI S Se en nso sors rs A Acce ccelera lerato tor r M Me em mo ory ry Interface IP (N (NP PU) U) E Em mb be ed dd de ed d 29% P
Slide 122: 3rd Party Design IP Market: 11% 2015-2023 CAGR
rd 3 Party Design IP Market: 11% 2015-2023 CAGR 2015 Semi IP Market 2023 Semi IP Market Other 8% Other 12% Foundation IP 15% Foundation IP Processor IP 14% Processors 48% Processors: 9% CAGR 56% Interfaces Interfaces 18% 29% 2015 Design IP Market: $3.0B* 2023 Design IP Market: $7.0B* * Synopsys IP C
Slide 123: Synopsys 3rd Party IP Market Share Growth
rd Synopsys 3 Party IP Market Share Growth 9% Market Share Gain 24.0% 22% 21.0% 18.0% 15.0% 12.0% 13% 9.0% 6.0% 3.0% 0.0% 2015 2016 2017 2018 2019 2020 2021 2022 2023 * Source: IP Nest, 2015-2024 (preliminary) Reports © 2024 Synopsys, Inc. rd Synopsys 3 Party IP Market Share
Slide 124: Synopsys Design IP: The World's Broadest IP Portfolio
Synopsys Design IP: The World’s Broadest IP Portfolio • 25 years of investment and commitment CPU GPU • ~25% of Synopsys revenue, ~$1.54B in 2023 Cluster Cluster • #2 IP provider wo Bus Fabrrldw ics ide AI Sensors Accelerator Memory • Leader in interface IP (NPU) Embedded Processors • Leader in foun
Slide 125: Synopsys IP: Strategic Growth for Years
Synopsys IP: Strategic Growth for 25 Years Synopsys IP Revenue Sensors AI Accelerators (NPUs, DSP) C CP PU U GPU C Clus lustte er r Cluster Security Processors CUSTOMER LOGIC B Bu us s Fab Fabr ric ics s Foundation IP (Std Cells, Memories) AI AI S Se en ns so or rs s A Ac cc ce eler lera atto or r M
Slide 126: Synopsys Expands IP Portfolio with Acquisition of Intrinsic ID
N E W ! Synopsys Expands IP Portfolio with Acquisition of Intrinsic ID Adds Production-Proven PUF IP to Synopsys’ Semiconductor IP Portfolio Synopsys Expands Semiconductor IP Portfolio Physical Unclonable Function (PUF) IP complements Synopsys’ With Acquisition of Intrinsic ID extensive IP portfolio
Slide 127: A Decade of Scaling: >10X Operating Leverage
A Decade of Scaling: >10X Operating Leverage Synopsys Design IP Revenue >5X Revenue Growth 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 Synopsys Design IP OM% >2X Ops Margin % Increase 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 © 2024 Synopsys, Inc. 128 10X Operating Leverage
Slide 128: IP Growth Drivers
IP Growth Drivers Silicon Accelerated Multi-Die Outsourcing Proliferation March to Pervasive Angstroms AI Five Factors Driving More Use of Synopsys IP © 2024 Synopsys, Inc.
Slide 129: More Silicon in More Markets Drive Advanced Design Starts
More Silicon in More Markets Drive Advanced Design Starts 2023 2024E 2025E 2026E 2027E 2028E 2029E 2030E HPC/AI Automotive Mobile Consumer/IoT Each Advanced Design Drives Multi-Million $ IP Opportunity © 2024 Synopsys, Inc. 16nm and smaller nodes. Source: Synopsys Internal Number of Design Starts
Slide 130: Moore's Law Marches On: 3-nm Ramping, 2-nm Starting
Moore’s Law Marches On: 3-nm Ramping, 2-nm Starting 16-nm 7-nm 5-nm 3-nm 2-nm 2024E 2018 Advanced Processes Drive Higher IP ASPs © 2024 Synopsys, Inc. Source: Synopsys Internal Pre-Sales Designs by Node
Slide 131: Silicon Complexity Exploding
Silicon Complexity Exploding Software Defined Systems: SoCs Shifting from Compounds Silicon Complexity Monolithic to Multi-Die Designs Pervasive Intelligence: Explosion of Heterogenous Complexity March to Trillions of Transistors: Expanding System Functionality © 2024 Synopsys, Inc.
Slide 132: Multi-Die Drives IP Growth
Multi-Die Drives IP Growth More Design Starts Multi-Die Designs More Interfaces More IP in Multiple Foundries More IP in Multiple Nodes Multi-Die Drives Design Starts, More IP Opportunities © 2024 Synopsys, Inc.
Slide 133: Pervasive AI is Driving Insatiable Need for Data Processing
Pervasive AI is Driving Insatiable Need for Data Processing 3.5 CPU Core Count Memory channel BW per core 3 2.5 INCREASING 2 GAP 1.5 1 0.5 0 2012 2014 2016 2018 2020 © 2024 Synopsys, Inc. Source: Meta, OCP Summit Presentation Nov 2021 Source: Standards Bodies Normalized to growth rate
Slide 134: Pervasive AI is Driving Insatiable Need for Data Processing
Pervasive AI is Driving Insatiable Need for Data Processing CPU Core Count Memory channel BW per core 3.5 USB PCIe S Stan tandards dards DDR Stand HBM Standards ards USB4 v2 1800 250 600 90 3 HBM4 PCIe 7.0 MRDIMM v2 1600 80 500 2.5 200 1400 70 HBM3E 1200 400 INCREASING 60 2 MRDIMM v1 150 GAP HBM3 10
Slide 135: Pervasive AI is Driving Insatiable Need for Data Processing
Pervasive AI is Driving Insatiable Need for Data Processing DDR Standards HBM Standards CPU Core Count Memory channel BW per core 3.5 250 1800 HBM4 MRDIMM v2 1600 200 HBM3E 1400 3 MRDIMM v1 1200 150 HBM3 1000 DDR5 5200 100 800 HBM2E HBM2E+ 2.5 600 DDR5 HBM2+ HBM2 DDR4 50 HBM DDR3 400 DDR2 200 INCREA
Slide 136: New Customers: System Companies Developing SoCs
New Customers: System Companies Developing SoCs % IP Revenue from System Companies % of Revenue from Systems Companies Steadily Growing Up 50% over 5 years Leading Shift to Multi-Die Packages FY18 FY19 FY20 FY21 FY22 FY23 System Companies: Green Fields for IP Source: Synopsys Internal © 2024 Synopsy
Slide 137: Supply Chain Resilience: Optionality and Optimality
Supply Chain Resilience: Optionality and Optimality Synopsys Broad IP Portfolio: The On-Ramp to Foundries © 2024 Synopsys, Inc.
Slide 138: Core vs Context: Established Companies Buying More IP
Core vs Context: Established Companies Buying More IP 100% 90% 24% 31% 35% 36% 80% 52% 70% 60% 50% 40% 76% 69% 65% 64% 30% 48% 20% 10% 0% Interface IP Processor IP Foundation IP Security IP In-Chip & PVT Monitoring IP Obtained from 3rd-party IP exists internally More Growth Potential With More Outso
Slide 139: What Matters in Selecting IP Vendor
What Matters in Selecting IP Vendor: Top 10 Extremely Important Quality of the IP 89% Understand Our Use Case/Application 88% Security 87% Customer Service/Support 85% Licensing Terms 83% Level of Engineering Expertise/Knowledge 80% Best PPA 80% Features Match Application Requirements 76% Vendor Rep
Slide 140: And How Does Synopsys Stack Up?
And How Does Synopsys Stack Up? Which of the following do you believe has the/is the… Best IP Highest Quality IP Best IP Support Industry Leader for IP Synopsys 35% 36% 37% 40% Competitor A 17% 12% 14% 10% Competitor B 16% 16% 13% 15% Competitor C 9% 13% 7% 7% Competitor D 8% 5% 8% 5% Competitor E 5
Slide 141: Here is What our Customers & Partners Have to Say
Here is What our Customers & Partners Have to Say Synopsys provides We know they Synopsys is technology to innovate, will be there to help supporting us to… build “ ““ speed design time & us achieve our automotive systems reduce risk – our most best designs. with the highest levels recent autopilot
Slide 142: Here is What our Customers & Partners Have to Say
Here is What our Customers & Partners Have to Say Synopsys’ broad IP Synopsys…our Our collaboration with portfolio helps chip primary IP partner, Synopsys leads “““ designers achieve first- has benefited our customers to their pass silicon success. mutual customers by fastest path to silicon providi
Slide 143: IP Growth Drivers
IP Growth Drivers Accelerated Silicon Multi-Die Proliferation Outsourcing March to Pervasive Angstroms AI © 2024 Synopsys, Inc.
Slide 144: IP Growth Drives Revenue Growth
IP Growth Drives Revenue Growth Accelerated Silicon Multi-Die Proliferation Outsourcing March to Pervasive Angstroms AI More Designs Faster Interfaces Higher ASPs More Outsourcing Sustainable Mid-Teens Growth © 2024 Synopsys, Inc.
Slide 145: Synopsys IP Scale: A Sustainable Advantage
Synopsys IP Scale: A Sustainable Advantage Wins over last 5 Years 10,000 Unique IP titles 8,100 Synopsys engineers developing IP 6,300 Process technologies down to 2nm 380 Foundries supported worldwide by Synopsys IP 30 © 2024 Synopsys, Inc.
Slide 146: In Summary
In Summary rd • Vibrant 3 party IP market with strong growth vectors • Synopsys leadership in interface IP, foundation IP & growing processor IP opportunity • High quality, best support, broadest IP portfolio • 25 years, ~25% of Synopsys • Resilient business model Sustainable Mid-Teens Revenue Growt
Slide 147: Thank You
SYNOPSYS” Our Technology, Your Inn THANK YOU
Slide 148: Our Technology, Your Innovation
SyNOPsys' Our Technology, Your Innovation”
Slide 149: Financial Overview
Financial Overview Shelagh Glaser Chief Financial Officer
Slide 150: We Do What We Say – Consistent Business Execution
We Do What We Say – Consistent Business Execution… 1 1 Revenue Non-GAAP Op. Margin Non-GAAP EPS $5.8B $11.19 35.1% 33.0% $5.1B 30.5% $8.90 28.0% $4.2B $3.7B $6.84 $5.55 FY20 FY21 FY22 FY23 FY20 FY21 FY22 FY23 FY20 FY21 FY22 FY23 ✓✓✓✓✓✓✓✓✓✓✓✓ Exceed / Met Guidance 1. See appendix for a reconciliation
Slide 151: Track Record of Resilient, Profitable Growth
…with Track Record of Resilient, Profitable Growth… 1 1 Revenue Non-GAAP Op. Margin Non-GAAP EPS FY23 FY23 FY23 $5.8B 35.1% $11.19 17% ~700 bps 26% CAGR Expansion CAGR FY20 FY20 FY20 $3.7B 28.0% $5.55 1. See appendix for a reconciliation of non-GAAP operating margin and non-GAAP EPS to their most di
Slide 152: …that has Accelerated Over Time
…that has Accelerated Over Time… Revenue Non-GAAP EPS 17% | 26% 1 FY20–23 CAGR 10% | 13% 1 FY10–20 CAGR FY10 FY11 FY12 FY13 FY14 FY15 FY16 FY17 FY18 FY19 FY20 FY21 FY22 FY23 1. See appendix for a reconciliation of non-GAAP EPS CAGR to its most directly comparable measure reported under GAAP as well
Slide 153: Leading to Shareholder Value Creation Outperformance
…Leading to Shareholder Value Creation Outperformance Synopsys outperformed 1 3-Year TSR Performance 6 out of 7 “Magnificent 7” 2 stocks over the last three years Magnificent 7 (3-Year TSR) 140% 2 136% Magnificent 7 67% SOXX S&P 500 30% S&P 500 20% Mar-21 Sep-21 Mar-22 Sep-22 Mar-23 Sep-23 Mar-24 NA
Slide 154: A High-Quality Business Portfolio
A High-Quality Business Portfolio FY23 Revenue Design Automation Design IP SIG Total in Application in IP in EDA #1 #2 #1 Software Testing Revenue CAGR 17% 21% 15% 18% (FY21–FY23) Operating Margin 1 1 1 2 38.1% 34.5% 14.5% 35.1% (FY23) Note: Figures based on Synopsys FY results in its 10-K as filed
Slide 155: Generating Strong Unlevered Free Cash Flow and Margins
Generating Strong Unlevered Free Cash Flow and Margins 1 1 Free Cash Flow Free Cash Flow Margin $1.6B FY23 $1.5B 26% $1.4B $0.8B ~330bps 1 Expansion FY20 23% FY20 FY21 FY22 FY23 1. See appendix for a reconciliation of free cash flow and free cash flow margin expansion to their most directly comparab
Slide 156: Driving Above Market Revenue Growth and Non-GAAP Margin Expansion
Driving Above Market Revenue Growth and Non-GAAP Margin Expansion 2 Revenue CAGR (FY21-23) Operating Margin Expansion (FY21-23) SIG 21% Design IP 17% 15% Design Automation ~14% ~13% EDA ~10% IP TAM SIG TAM 1 Growth TAM 1 Growth 1 Growth FY21 Design Design SIG FY23 Automation IP 1. Represents FY21-FY
Slide 157: Design Automation: Innovation to Drive Above Market Growth
Design Automation: Innovation to Drive Above Market Growth Design Automation Key EDA Growth Drivers Industry-Leading Growth 1 Revenue | Adj. Op Margin SNPS EDA Long-Term Objective March to Angstroms FY23: $3.8B | 38.1% Double-digit growth above market Multi-Die ~2% ~12% AI 17% CAGR Potential EDA TAM
Slide 158: Design IP: Profitable and Growing
Design IP: Profitable and Growing Resilient Business Model Design IP Key IP Growth Drivers Industry-Leading Growth 1 Revenue | Adj. Op Margin SNPS IP Long-Term Objective Silicon Proliferation FY23: $1.5B | 34.5% Mid-teens growth above market March to Angstroms Multi-Die 21% CAGR ~15% ~430bps IP TAM
Slide 159: Creating a Leader in Silicon to Systems Design Solutions
Creating a Leader in Silicon to Systems Design Solutions SIG Design Design Simulation & Automation IP Analysis #1 #1 #2 Industry Leader in EDA in IP in AST 1 1 ~$6B FY23 Revenue ~$2B FY23 Revenue Building on our successful seven-year partnership 1. Based on Synopsys FY results in 10-K as filed with
Slide 160: Attractive Financial Benefits Drive Shareholder Value
Attractive Financial Benefits Drive Shareholder Value High Quality Revenue High Margin Better Together Expected to add high quality, Expected to immediately Expected to add high quality, durable revenue stream expand margins durable revenue stream ~125bps ~75 bps ~$400M ~$400M ~$8B Year 1 Non-GAAP Y
Slide 161: Highly Achievable, Identified Synergies and Potential for More
Highly Achievable, Identified Synergies and Potential for More ~$400M ~$400M ~$1B+ of run-rate cost synergies of run-rate revenue of annual revenue synergies expected by year 3 synergies expected by year 4 expected over longer-term • Streamlining and realizing the benefits • Integration of multi-phy
Slide 162: Identified and Achievable Drivers of Synergies
Identified and Achievable Drivers of Synergies Significant potential for additional revenue synergies: • Further penetration beyond Semiconductor / High-Tech Revenue: ~30% • New joint innovative ~$1B+ Revenue: system solutions (e.g., ~$400M ~70% digital twin, functional safety solutions) ~20% Cost:
Slide 163: Strong Combined Balance Sheet with Strong Free Cash Flow Generation
Strong Combined Balance Sheet with Strong Free Cash Flow Generation Supporting Financial Flexibility Expected Rapid Financial Flexibility for Disciplined Capital Allocation 1 Deleveraging • Expect rapid deleveraging to <2x within 2 Debt / Adj. EBITDA years post close Deleveraging • Long-term gross l
Slide 164: Committed to a Successful Integration
Committed to a Successful Integration Highly complementary Dedicated team to execute integration post-close businesses Objectives Key Functional Areas Common secular trends and Continued successful execution customer needs ❑ Engineering Maintain strong customer ❑ GTM Shared deep tech and engagements
Slide 165: Disciplined Capital Allocation: Strategic Portfolio Decision
Disciplined Capital Allocation: Strategic Portfolio Decision Compelling growth opportunities in Design Automation and Design IP Announced in Q4’23 exploration of strategic alternatives for Software Integrity Group, the leader in application security testing Completed a comprehensive review of altern
Slide 166: FY 2024 Guidance Update
FY 2024 Guidance Update Prior Guidance (incl. SIG) Updated Guidance (excl. SIG) $6,570 - $6,630 $6,060 - $6,120 12.4% - 13.5% $5,843 14.0% - 15.1% $5,318 Positive impact to growth and Revenue profitability ✓ Strength FY23 FY24E FY23 FY24E in Design Automation and Design $13.47 - $13.55 IP $12.86 - $
Slide 167: Long-Term Financial Objectives
1 Long-Term Financial Objectives Combined company long-term, multi-year objectives Revenue Non-GAAP Op. Free Cash Flow Non-GAAP EPS Margin Industry-leading Long-term unlevered Non-GAAP EPS double-digit growth free cash flow margins growth in the Long-term non-GAAP 2 2 in mid 30s high-teens range ope
Slide 168: Committed to Creating a Smart Future Together
I n d u y s t t i r r y u c S e s u r s e t b a i y n C a b i l i t y S o e c l i p a o l e Committed to Creating a Smart Future Together Enabling customers to innovate for a greener world Reducing our carbon footprint with science-based targets Empowering global talent through a culture of innovati
Slide 169: Confidence in Trajectory
Confidence in Trajectory Delivering outsized shareholder value Industry-leading, resilient growth Expanding and accelerating margins Balanced, disciplined capital allocation priorities © 2024 Synopsys, Inc.
Slide 170: Thank You
SYNOPSYS” Our Technology, Your Inn THANK YOU
Slide 171: Our Technology, Your Innovation
SyNOPsys' Our Technology, Your Innovation”
Slide 172: Join Us at SNUG Pub!
JOIN US AT SNUG PUB! Synopsys Confidential Information
Slide 173: Our Technology, Your Innovation
SyNOPsys' Our Technology, Your Innovation”
Slide 174: Appendix
Appendix © 2024 Synopsys, Inc. 175
Slide 175: Our Revised FY 2024 Guidance
Our Revised FY 2024 Guidance Prior Guidance (incl. SIG) Updated Guidance (excl. SIG) $6,060 - $6,120 $6,570 - $6,630 Revenue ($M) +12.4% - 13.5% +14.0% - 15.1% 1 Non-GAAP Expenses $4,140 - $4,180 $3,755 - $3,795 ($M) Non-GAAP Other Income & $24 - $28 $32 - $36 Expense Net ($M) 15% 15% Non-GAAP Tax R
Slide 176: Our Revised Q2 2024 Guidance
Our Revised Q2 2024 Guidance Prior Guidance (incl. SIG) Updated Guidance (excl. SIG) $1,560 - $1,590 $1,425 - $1,455 Revenue ($M) +11.8% - 14.0% 12.8% - 15.2% 1 Non-GAAP Expenses $1,005 - $1,015 $905 - $915 ($M) Non-GAAP Other Income & $2 - $4 $2 - $4 Expense Net ($M) Non-GAAP Tax Rate 15% 15% Fully
Slide 177: GAAP to Non-GAAP Reconciliation: Operating Income and Operating Margin
GAAP to Non-GAAP Reconciliation Operating Income and Operating Margin ($ in millions) 2020 2021 2022 2023 Margin $ Margin % Margin $ Margin % Margin $ Margin % Margin $ Margin % GAAP operating income and operating margin $620.1 16.8% $734.8 17.5% $1,162.0 22.9% $1,269.3 21.7% Adjustments: Amortizati
Slide 178: GAAP to Non-GAAP Reconciliation: Net Income per Diluted Share
GAAP to Non-GAAP Reconciliation Net Income per Diluted Share 2018 2019 2020 2021 2022 2023 2010 2011 2012 2013 2014 2015 2016 2017 GAAP net income per diluted share $1.56 $1.47 $1.21 $1.58 $1.64 $1.43 $1.73 $0.88 $2.82 $3.45 $4.27 $4.81 $6.29 $7.92 Adjustments: Amortization of intangible assets $0.3
Slide 179: GAAP to Non-GAAP Reconciliation: FY24 Updated Guidance Expenses
GAAP to Non-GAAP Reconciliation FY24 Updated Guidance: Expenses Prior Guidance (incl. SIG) Updated Guidance (excl. SIG) Q2'24 FY'24 Q2'24 FY'24 Low High Low High Low High Low High ($ in millions) Target GAAP expenses $1,206 $1,226 $5,022 $5,079 $1,083 $1,103 $4,535 $4,592 Adjustments: Amortization o
Slide 180: GAAP to Non-GAAP Reconciliation: FY24 Net Income per Diluted Share
GAAP to Non-GAAP Reconciliation FY24 Updated Guidance: Net Income per Diluted Share Prior Guidance (incl. SIG) Updated Guidance (excl. SIG) Q2'24 FY'24 Q2'24 FY'24 FY’23 FY’23 Low High Low High Low High Low High GAAP net income per diluted share $7.92 $2.05 $2.16 $9.56 $9.74 $7.95 $2.01 $2.12 $9.47
Slide 181: Reconciliation of Unlevered Free Cash Flow and Related Metrics
Reconciliation of Unlevered Free Cash Flow and Related Metrics ($ in millions) FY2020 FY2021 FY2022 FY2023 Cash flow from operating activities $991 $1,493 $1,739 $1,703 ( - ) Purchases of Property and Equipment (155) (94) (137) (190) ( - ) Capitalized Software Development Costs (4) (2) (2) (2) = Fre
Slide 182: Business Segment Reporting
1, 2 Business Segment Reporting UNAUDITED, IN MILLIONS FY 2021 FY 2022 FY 2023 Revenue by segment Design automation $2,754.7 $3,300.2 $3,775.3 % of total 65.5% 64.9% 64.6% Design IP $1,055.7 $1,315.5 $1,542.7 % of total 25.1% 25.9% 26.4% Software integrity $393.8 $465.8 $524.6 % of total 9.4% 9.2% 9