Synopsys, Inc. · NASDAQ:SNPS

Synopsys — Semiconductor Technology Academic Research Center (STARC) — Design Automation Conference 2006

13 slides from Synopsys's conference presentation, Jul 26, 2006

  1. Slide 1: ICC in STARCAD-21

    ICC in STARCAD-21 July 26th, 2006 Nobuyuki Nishiguchi VP and General Manager Semiconductor Technology Academic Research Center (STARC) Copyright © Semiconductor Technology Academic Research Center, 2006, All rights reserved. Design Automation Conference, 2006, San Francisco

  2. Slide 2: Industry Change for System LSI

    Industry Change for System LSI Value up the design platform in System LSI as industry standard Marketing and new products in order to create new markets Enterprise Focusing on differentiating market segment 公共分野 民生分野 Market oriented design platform 産業分野 Difficulties in design due to nanometer techno

  3. Slide 3: STARCAD-21 Release History

    STARCAD-21 Release History RTLtoGDS2 Design Methodology in 90nm process generation V3.0 Design Margin Reduction n g y ig V2.5 Design Efficiency lo es do D Design TAT ho nt V2.0 Reduction e t ie M f f ic Low Power E V1.5 gh Design Hi V1.0 Hierarchical Basic Design e s ign d ard d gy Basic Design Stan

  4. Slide 4: STARCAD-21 Methodology

    STARCAD-21 Methodology RTL to GDS2 design methodology in 90nm and below RTL Design ：Check and go ：Prediction and prevention Constraints process technology Acceptance Straight forward design methodology RTL Planning Estimation Sign-off rule, Analysis method Library, Design guide line, Physical synthe

  5. Slide 5: Pegas (Synopsys Base Flow) Activities and tools

    Pegas (Synopsys Base Flow ) Activities and tools V1.0β V1.0 V1.5 V2.0 V2.5 V3.0 DC DC DC DC DC DC FPC JXT JXT JXT JXT JXT PhC PhC PhC PhC PhC ICC Astro Astro Astro Astro Astro Margine Basic flow Hierarchy Low Power High efficiency Reduction Clock Plan Hierrchy Pseudo Hierarchy Hierarchical Design MI

  6. Slide 6: Achievements in Pegas V3.0

    Achievements in PegasV3.0 IC ICCompiler CompilerIntroduction Introduction 2006.06 Margin Marginreduction reduction Concurrent ConcurrentMM-opt MM-opt DC Topographical DC Topographical Hierarchical Design Hierarchical Design No Noincremental incrementalSynthesis Synthesis Multi MultiVDD VDD Correlati

  7. Slide 7: ICC VS PhC/Astro (HSC03 (mpeg))

    ICC VS PhC/Astro（HSC03(mpeg)) „ RunTime : -48% １Mode Optimization „ Memory : +35% ⇒ There is on-going effort in ICC to reduce memory usage. 48% 35%(dr-opt) Copyright © Semiconductor Technology Academic Research Center, 2006, All rights reserved. Design Automation Conference, 2006, San Francisco 7

  8. Slide 8: ICC Concurrent MM Optimization (Risc-Core)

    ICC Concurrent MM Optimization (Risc-Core) ５CORNER MAX.db RC_4 ６ MODE Function scan_shift MIN.db RC_4 „ Concurrent MM (6 modes, 2 corners) MAX.db RC_8 ctrl_shift ctrl_capture MIN.db RC_9 xdbist_shift xdbist_capture MAX.db RC_9 ICC 450.00 Timing Error：1403 Hold Number of Errors Setup 400.00 Concurren

  9. Slide 9: ICC QoR [RunTime]

    ICC QoR［RunTime］ „ QoR of ICC V1.1-SP1 is little bit better than ICC V1.0. „ QoR of ICC V1.1-SP1 is better than PhC/Astro at high speed area. PC/Astro=4ns did not finished. 15 PCAstro 15 PCAstro ICCV10 ICCV10 12 V1.1SP1 12 V1.1SP1 RunTime[hour] RunTime[hour] 9 9 6 6 3 3 0 0 8ns 6ns 5ns 4ns 55% 65% 7

  10. Slide 10: ICC QoR [Slack] (ACORE)

    ICC QoR［Slack］ （ACORE） „ Slack reduction : 40%～102% „ The QoR of ICC V1.1-SP1 is same with ICC V1.0. 0.5 PCAstro 0.5 ICCV10 0.3ns V1.1SP1 0.0 0.0 Slack[ns] Slack[ns] -0.5 -0.5 PCAstro -1.0 -1.0 ICCV10 V1.1SP1 -1.5 -1.5 8ns 6ns 5ns 4ns 55% 65% 75% FP-Utilization=55% Clock Period[ns] FP-Utilization Cl

  11. Slide 11: ICC QoR [Area] (ACORE)

    ICC QoR［Area］ （ACORE） „ Cell area of ICC V1.1-SP1 is smaller than ICCV1.0. „ Cell area of ICC is smaller than Astro in timing critical zone. Cell Area 400000 PCAstro 400000 380000 ICCV10 380000 360000 V1.1SP1 360000 340000 Area 340000 Area 320000 320000 300000 PCAstro 300000 280000 ICCV10 280000 V1.

  12. Slide 12: STARCAD-21 TAT Reduction

    STARCAD-21 TAT Reduction （％） 120 Major Achievement Design TAT: 100 •Floorplan improvement 1/6 Reduction! •Incremental method •Ｗｈａｔ－Ｉｆ analysis 80 •Hand-off rule •Reduction of sign-off corners 60 •Noise accuracy improvement •Integration with logic BIST •Multi mode analysis 40 •Design margin reduction

  13. Slide 13: Summary

    Summary „ STARCAD-21 is the de-facto standard design methodology for 90nm and below system LSI „ IC Compiler in STARCAD-21 delivers z Reduced TaT (MCMM, signoff correlation) z Improved QoR (timing, power, area) „ STARC is developing DFM methodology called STARCAD-CEL STARC Aid your Design with Certi

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