Slide 1: Maximizing Fabric Performance (FMAX) for AMD Versal Adaptive SoCs
Maximizing Fabric Performance (FMAX) for AMD Versal Adaptive SoCs WEBINAR PRESENTATION
Slide 2: Maximizing Fabric Performance (FMAX) for AMD Versal Adaptive SoCs
Maximizing Fabric Performance (FMAX) for AMD Versal Adaptive SoCs Ehab Mohsen, Senior Product Marketing Manager Ron Plyler, Senior Technical Marketing Manager Benoit Payette, Senior Technical Marketing Manager
Slide 3: Agenda
[Public] AGENDA AMD Versal Architecture & Methodology Overview Understanding Changes in Programmable Logic Architecture “Clean” Your Design: Migration Checklist “Baselining” for Timing Closure Advanced QoR Techniques to Meet FMAX Targets 3
Slide 4: AMD Versal Adaptive SoCs: Heterogenous Acceleration with Hardened IP
[Public] AMD Versal Adaptive SoCs: Heterogenous Acceleration with Hardened IP Heterogeneous Engines Heterogeneous Acceleration Diverse compute engines Breakthrough Integration of Hard IP ASIC perf/watt for bandwidth-intensive functions FPGA Fabric for Differentiation Hardware adaptable for custom al
Slide 5: AMD Versal Architecture Overview
[Public] AMD Versal Architecture Overview Programmable Logic Scalar Engines • Re-designed for AMD Versal architecture AI Engines • Tunable for power vs. performance • Application & real-time processing subsystem • Novel vector processing array architecture • Dual Arm Cortex® -A72 8x Arm Cortex-A78
Slide 6: 1st Generation AMD Versal Portfolio
[Public] 1st Generation AMD Versal Portfolio Optimized for the Application Domain AI Core Series AI Engines for AI & DSP compute for wireless & cloud AI Edge Series AI Engines for AI & DSP performance/watt for edge markets Prime Series Mid-range series for broad range of applications Premium Series
Slide 7: First Generation Second Generation
[Public] First Second Generation Generation 7 |
Slide 8: Requires a System Design Methodology Coupled with FPGA QoR Best Practices
[Public] Requires a System Design Methodology Coupled with “FPGA” QoR Best Practices System Partitioning & Algorithm Mapping Partition design across engines (if applicable) AMD Vitis Embedded for Arm® subsystem Intuitive IDE, traditional eclipse-based flows Hardware-Only Embedded System System
Slide 9: AMD Versal Adaptive SoCs Can Involve a Breadth of Developers
[Public] AMD Versal Adaptive SoCs Can Involve a Breadth of Developers System Architect PCB Designer FPGA Developer Embedded Developer DSP Developer AI Developer Today’s Focus: Traditional FPGA Design with Programmable Logic 9 |
Slide 10: AMD Versal Architecture: Changes from Previous Generations
AMD Versal Architecture: Changes from Previous Generations
Slide 11: FPGA Fabric: Higher Density Per Configurable Logic Block (CLB)
[Public] FPGA Fabric: Higher Density Per Configurable Logic Block (CLB) • 4X logic per configurable logic block (CLB): 8 32 LUTs, 16 64 slice flip-flops • Reduces use of external routing resources for optimal results 16nm AMD UltraScale+ CLB 7nm AMD Versal CLB: 4X Density 11 |
Slide 12: Breadth of CLB Enhancements to Improve Utilization
[Public] Breadth of CLB Enhancements to Improve Utilization AMD Versal Configurable Logic Block Greater LUT LUT-to-LUT New Internal Packing Cascade Carry Chain Interconnect Reduces • Intra-CLB Interconnect Routing Congestions Greater packing of logic per CLB Intra-CLB • Dual LUT Functions w/6 Output
Slide 13: Other Fabric-Related Changes in AMD Versal Adaptive SoCs
[Public] Other Fabric-Related Changes in AMD Versal Adaptive SoCs Embedded RAM DSP Clocking • More UltraRAM aspect ratios • Improved performance across data types • Granular control to minimize clock skew • Fewer Block RAM aspect ratios • Support for 32-bit floating point • Optimal performance acros
Slide 14: Programmable Network-on-Chip: New Design Paradigm
[Public] Programmable Network-on-Chip: New Design Paradigm AMD Versal Device High Bandwidth Pipe Across Device AI Engines • Terabits/sec bandwidth (34.56GB/s per NoC Lane1) Thin Horizontal NoC (2 Lanes) High Bandwidth • Connects engines and critical hard IP2 Pipe Helps Meet Timing on Critical paths
Slide 15: Design Starts with CIPS and NoC Setup
[Public] Design Starts with CIPS and NoC Setup • CIPS for Platform Configuration CIPS • Dedicated IP for Control, Interfaces, & Processing System (CIPS) (Platform Configuration) IP Integrator Design Creation • Instantiate through IP Integrator RTL IP Block Design • Contains platform management contr
Slide 16: Maximize Performance with a Systematic Migration Process
[Public] Maximize Performance with a Systematic Migration Process 16 |
Slide 17: Clean Your Design Migration Checklist
Clean Your Design Migration Checklist
Slide 18: Checklist for Migrating from AMD UltraScale+ to Versal Designs
[Public] Checklist for Migrating from AMD UltraScale+ to Versal Designs Use the Hard IP Maximize use of hard IP for optimal performance/watt Plan for replacement of certain soft IP, e.g., memory controllers, DMA Carry Logic & Carry Logic AND Wide Multiplexers Wide Mux’s Resynthesize RTL to avoid leg
Slide 19: Carry Chain Logic
[Public] Carry Chain Logic • Different implementation in AMD Versal CLB (carry multiplexer and summation logic pushed into LUT) • Former “CARRY8” has been replaced by “LOOKAHEAD8” • Legacy instantiations of CARRY8 may lead to delay QoR degradation, avoid importing synthesized netlists AMD UltraScale
Slide 20: Wide Multiplexer Functionality
[Public] Wide Multiplexer Functionality • AMD Versal CLB eliminates dedicated wide multiplexers (MUXFs) previously in AMD UltraScale+ CLB • Higher LUT resources and intra-CLB routing in AMD Versal CLB to implement similar functionality • Equivalent function may use more logic levels but use fewer CL
Slide 21: Clocking Enhancements Minimize Skew to Maximize Performance
[Public] Clocking Enhancements Minimize Skew to Maximize Performance AMD Versal Clocking Architecture Breadth of Enhancements to Reduce Skew for FMAX • Similar segmented clock network Horizontal NoC Segmented Similar clocking elements (e.g., MMCM, XPLL) Clock Routing Similar to AMD • BUFG_Fabric for
Slide 22: Clocking Migration
[Public] Clocking Migration • AMD Vivado software can’t always instantiate primitives to optimal AMD Versal equivalent • Instantiate clocking elements via Clocking Wizard (preferred), global TCL script, inference (if constraints permit) • Leverage new primitives, e.g., MBUFG (division: /1, /2, /4, /
Slide 23: Balanced Selection of Block RAM and UltraRAM Aspect Ratios
[Public] Balanced Selection of Block RAM and UltraRAM Aspect Ratios • What Changed: Supported Aspect Ratios • UltraRAM aspect ratios expanded, initialization support • Block RAM ratios reduced to wider bit-widths (most common use cases) Block RAM UltraRAM • Hardened FIFO removed (greater area effici
Slide 24: AMD Versal DSPs: Enhanced Performance & Backward Compatible
[Public] AMD Versal DSPs: Enhanced Performance & Backward Compatible • Enhanced multipliers, accumulators, DSP-to-Fabric connectivity (super-tiles) to maximize compute per block • New native supports for INT8 Dot Product, Complex Multiply, and Single-Precision Floating Point • Code portable from AMD
Slide 25: Other Attributes & Directives
[Public] Other Attributes & Directives • Remove previous optimization or debug attributes (e.g., dont_touch, max_fanout) • Revisit macros to align with latest enhancements (e.g., RAM XPM macros) Attribute to Remove Why dont_touch Can lead to bloated design mark_debug Can bloat design and retain unne
Slide 26: Ways to Quickly Identify Legacy Primitives
[Public] Ways to Quickly Identify Legacy Primitives (vs. Manual Process) 1. Use TCL command on Elaborated RTL view (see appendix for full command) 2. “Report Cell Usage” Section in synthesis report (lists primitives used) 3. “Transformation Summary” in AMD Vivado log file that lists logic transforms
Slide 27: Baseline Your Design: Back to Basics
Baseline Your Design: “Back to Basics”
Slide 28: What is Baselining?
[Public] What is Baselining? • A starting point that follows a set of guidelines to incrementally identify and fix timing issues • Avoid “dropping in” previous XDC file with I/O constraints, physical constraints, etc. • ‘Cut through the noise’ of having too many constraints which may obscure critica
Slide 29: Baseline Flow
[Public] Baseline Flow Clean Design 1. Run Synthesis on Clean Design (no constraints) – Initial design check: utilization, logic levels, etc. 1 Run Synthesis – Identify HDL issues for recoding leverage AMD templates 2. Constrain Clocks 2 Constrained All Clocks – Constrain all primary and generated
Slide 30: Constrain All Clocks after Synthesis
[Public] Constrain All Clocks after Synthesis 1 Synthesis 2 Clocks • Synthesize design without user constraints to generate netlist / design checkpoint (*.dcp) • Leverage Constraints Wizard to constrain primary and generated clocks • Report Clock Networks hierarchically navigate and constrain rema
Slide 31: No Unsafe Clock Domain Crossings
[Public] No “Unsafe” Clock Domain Crossings 1. Identifying unsafe CDC’s 3 CDC’s a) Report Clock Interaction: visually identify via AMD Vivado tool user interface b) Report Methodology” – enable setting to flag unsafe CDC’s c) Leverage TCL Script in Appendix to flag CDCs before full P&R implementatio
Slide 32: Synthesis Baselining: How to Meet Timing
[Public] Synthesis Baselining: How to Meet Timing • Start with default synthesis, and if timing not met, optimization techniques are available • Approaches range from automated to manual Synthesis 4 Timing • Preconfigured synthesis strategies, bottom-up synthesis, RTL modifications Preconfigured, Gl
Slide 33: Let QoR Assessment & QoR Suggestions Be Your Guide
[Public] Let “QoR Assessment” & “QoR Suggestions” Be Your Guide Automated Flows to Help Timing Closure RQA RQS Report QoR Assessment Report QoR Suggestions • Scores the design, predicts likelihood of meeting FMAX • Suggests compile strategies or directives to improve FMAX • Flags issues & potential
Slide 34: Leverage Different Types of Reporting for Timing Analysis
[Public] Leverage Different Types of Reporting for Timing Analysis Timing Summary Report Design Analysis Report • First line of defense to identify cell delay, route delay, clock skew • Gathers and analyzes logic, timing, physical characteristics • Comprehensive view of clocks, clock groups, CDC’s,
Slide 35: P&R Baselining: Evaluating at Every Stage
[Public] P&R Baselining: Evaluating at Every Stage • Evaluate slack at every implementation stage: Synthesis Met Timing • Focus on setup violations & large hold time violations 5 P&R • opt_design • logic optimizations (e.g., logic delays, # of logic levels) opt_design • Resolve setup violations < -.
Slide 36: Advanced QoR Techniques to Meet FMAX Targets
Advanced QoR Techniques to Meet FMAX Targets
Slide 37: Advanced Techniques to Resolve P&R Timing Violations
[Public] Advanced Techniques to Resolve P&R Timing Violations • If RQS not resolving issues, may need deeper analysis • Timing Report Design Analysis Report Load Design Checkpoint • Factors causing timing violations with Timing Violations Try report_qor_suggestions (RQS) 1. Logic Delay for automated
Slide 38: Move IP onto NoC when Possible
[Public] Move IP onto NoC when Possible Leverage NoC When Possible Saves Logic Resources, Alleviates Congestion • NoC is ideal when routes must travel across the device XPIO • AXI-based connectivity DDR Controller DDR Controller DDR Controller Horizontal NoC • By moving IP onto the NoC, designs can
Slide 39: Next Steps and Summary
Next Steps =e and Summary
Slide 40: Download the Latest AMD Vivado Design Suite
[Public] Download the Latest AMD Vivado Design Suite Ensure You Have the Latest Tool Capabilities for AMD Versal Devices Out-of-Box QoR Improvements User-Guided QoR Optimization Features Clocking (e.g., clock skew improvements for multi-SLR devices) Dynamic Function eXchange (DFX) Features
Slide 41: Core AMD Versal Design Methodology Guides
[Public] Core AMD Versal Design Methodology Guides System Integration & Validation Guide (UG1388) • Design Process Overview • Simulation Flows • Design Closure • System Performance Closure • Config & Debug • Validation Hardware, IP, Platform Development Guide (UG1387) • Design Planning • Design Crea
Slide 42: Breadth of Resources to Get Started
[Public] Breadth of Resources to Get Started Collateral & Docs On-Demand Courses Community Forums • AMD Versal Design Guide (UG1273) • Getting Started with AMD Versal Platform (Free) • Design Entry and IP Flows • AMD Versal Methodology Guide (UG949) • Designing with AMD Versal Adaptive SoC: Architec
Slide 43: Design Process Hub: Visually Organized Resources by Process
[Public] Design Process Hub: Visually Organized Resources by Process System Solution Board System HW, HW, IP,IP, andand Machine Learning & Planning Design Platform Dev & Data Science Embedded SW System Solution AI Engine Development & Planning Development Overview: Traditional Designs Traditional De
Slide 44: Migration Course Now Available
[Public] Migration Course Now Available Migrating from AMD UltraScale+ Devices to AMD Versal Adaptive SoCs • Development platforms for all developers • Review different migration approaches • System design planning and partitioning • Identifying and comparing functional blocks • Considerations for P
Slide 45: Summary
[Public] Summary Understand “Clean” Your Design Baseline for Apply Advanced Leverage the Architecture for Migration Timing Closure QoR Techniques Training Resources Reap the Benefits of AMD Versal Adaptive SoCs with QoR Best Practices 45
Slide 46: Calls to Action
[Public] Calls to Action • Download Presentation Slides (links and more resources in Appendix) • Learn More About AMD Versal portfolio at www.amd.com/versal • Download latest AMD Vivado Design Suite Release for latest features • Leverage training resources and methodology guides to get started 46 |
Slide 47: Disclaimer and Attributions
[Public] DISCLAIMER AND ATTRIBUTIONS DISCLAIMER Timelines, roadmaps, and/or product release dates shown in these slides are plans only and subject to change. The information contained herein is for informational purposes only and is subject to change without notice. While every precaution has been t
Slide 48: Appendix
[Public] APPENDIX TCL Command to Flag Unsafe Clock Domain Crossings TCL Command to Flag Primitives in Design Preconfigured Synthesis Strategy Settings to Improve Timing Synthesis Strategy Settings Known to Work for AMD Versal Architecture Out-of-Context, Bottom-Up Synthesis Addressing High Logic Del
Slide 49: TCL Script: Flag Unsafe CDC's during Place & Route
[Public] TCL Script: Flag Unsafe CDC’s during Place & Route • Useful technique to prevent running full P&R before CDC’s are defined • Avoids wasting time on implementing databases that are likely to fail timing due to CDC paths report_methodology –checks {TIMING-6 TIMING-7} –file opt_meth_checks.rpt
Slide 50: TCL Command to Flag Use of Primitives in Design
[Public] TCL Command to Flag Use of Primitives in Design • Instantiated primitives in RTL view are visible. Find them with the following command: show_objects -name find_1 [get_cells -hierarchical -filter { BOX_TYPE == "PRIMITIVE" } ] 50 |
Slide 51: Preconfigured Synthesis Strategies to Improve Timing
[Public] Preconfigured Synthesis Strategies to Improve Timing Useful Strategies for FMAX Options / Strategy Default Area Area Area Mult Alternate Performance Performance Runtime Optimized Optimized Threshold Routability Optimized Threshold Optimized (High) (Medium) DSP (High) Carry -flatten_hierarch
Slide 52: Synthesis Strategy Settings Known to Work for AMD Versal Architecture
[Public] Synthesis Strategy Settings Known to Work for AMD Versal Architecture GUI Settings • Three Target Strategies 1. AlternateRoutability 2. FewerCarryChains 3. PerformanceOptimized • 2 Modifications for each: • -control_set_opt_thresh = 16 • -shreg_min_size = 5 • Issue via GUI or TCL Command TC
Slide 53: Out-of-Context, Bottom-Up Synthesis
[Public] Out-of-Context, Bottom-Up Synthesis • Good practice to iterate on smaller modules before implementing the full design TOP • Target sub-modules that are >25K LUTs • Only constrain clocks and clock interactions for submodule (use wizards to help) TOP • Create custom synthesis run with ‘out_of
Slide 54: Addressing High Logic Delay
[Public] Addressing High Logic Delay General Logic Level Guidelines • Be sure to run opt_design first (significant optimizations) Rules of Thumb Only, varies by device & speed grade • How many logic levels vs. your target FMAX, see table Target FMAX # of Logic Levels • Consider the following 200MH
Slide 55: Address High Net Delay
[Public] Address High Net Delay AMD Versal BUFG_Fabric Fast Access to Clock Network (for non-clock signals) • Review Floorplan Constraints (if any) • Examine Pblocks (logic cell grouping) FPGA • Examine LOC (logic cell placement) Fabric • Address Highly Congested Regions Logic • Run report_design_an
Slide 56: Addressing High Clock Skew and Uncertainty (Highlights)
[Public] Addressing High Clock Skew and Uncertainty (Highlights) • Leverage New Multi-Clock Buffer (MBUFG) for Clock Division & sync CDC’s • Dedicated MBUFGs for Fabric • Avoid MMCM or PLLs for simple division (/1, /2, /4, /8) • Use Specific Clock Tree Type to optimize global clock skew • Three sett
Slide 57: AMDe
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