Marvell Technology, Inc. · NASDAQ:MRVL
Marvell Technology — Investor Day (June 2025)
124 slides from Marvell Technology's investor day presentation, Jun 17, 2025
Slide 1: Custom AI Investor Event
=| MARVELL’ Custom AI Investor Event June 17, 2025
Slide 2: Ashish Saran, SVP, Investor Relations
Ashish Saran SVP, Investor Relations
Slide 3: Forward-looking statements
Forward-looking statements Except for statements of historical fact, this presentation contains forward-looking statements (within the meaning of the federal securities laws) including, but not limited to, statements related to market trends and to the company’s business and operations, business opp
Slide 4: Non-GAAP financial measures
Non-GAAP financial measures ▪ During this presentation, we may refer to certain financial measures on a U.S. non-GAAP basis. ▪ We believe that the presentation of non-GAAP financial measures provides important supplemental information to management and investors regarding financial and business tren
Slide 5: Agenda
Agenda Matt Murphy Chairman and Chief Executive Officer Chris Koopmans Chief Operating Officer Nick Kucharewski SVP and GM, Cloud Platform Sandeep Bharathi Chief Development Officer Will Chu SVP and GM, Custom Cloud Solutions Q&A © 2025 Marvell. All righ ts reserved. 5
Slide 6: © 2025 Marvell. All righ ts reserved.
© 2025 Marvell. All righ ts reserved. 6
Slide 7: Matt Murphy
Matt Murphy Chairman and Chief Executive Officer
Slide 8: Cloud-optimized silicon
Cloud-optimized silicon © 2021 Marvell. All righ ts reserved. 8 © 2025 Marvell. All righ ts reserved. 8
Slide 9: © 2025 Marvell. All righ ts reserved.
© 2025 Marvell. All righ ts reserved. 9
Slide 10: AI infrastructure buildout drives incredible growth
AI infrastructure buildout drives incredible growth Top 4 U.S. hyperscaler CAPEX 46% CAGR $327B $248B $153B CY23 CY24 CY25 Source: public information © 2025 Marvell. All righ ts reserved. 10
Slide 11: Emerging hyperscalers rising fast
Emerging hyperscalers rising fast Models Applications Sovereign AI STARGATE ••• ••• ••• © 2025 Marvell. All righ ts reserved. 11
Slide 12: AI infrastructure buildout drives incredible growth
AI infrastructure buildout drives incredible growth Top 4 U.S. hyperscaler CAPEX 46% CAGR $327B $248B $153B CY23 CY24 CY25 Source: public information © 2025 Marvell. All righ ts reserved. 12
Slide 13: AI infrastructure buildout drives incredible growth: total data center CAPEX
AI infrastructure buildout drives incredible growth Total data center CAPEX 51% $593B CAGR $435B STARGATE $260B CY23 CY24 CY25 Source: public information, Dell’Oro © 2025 Marvell. All righ ts reserved. 13
Slide 14: To reach $1 trillion by 2028
To reach $1 trillion by 2028 $1,022B 20% CAGR $593B $435B STARGATE $260B CY23 CY24 CY25 CY28 Source: public information, Dell’Oro © 2025 Marvell. All righ ts reserved. 14
Slide 15: Marvell data center TAM
Marvell® data center TAM Data center TAM: AI Day April 2024 $75B 29% Accelerated CAGR $42.9 custom compute 45% CAGR $21B $12.0 Switching 15% CAGR $6.6 $6.1 $13.9 Interconnect 27% CAGR $4.3 Storage 7% CAGR $4.2 $5.9 CY23 CY28 Source: 650 Group, CignalAI, Dell’Oro, LightCounting, and Marvell estimates
Slide 16: Marvell data center TAM
Marvell data center TAM $94B $75B Accelerated $55.4 custom compute 53% CAGR $42.9 +26% larger $13.2 Switching 17% CAGR $21B $12.0 $6.6 $19.0 Interconnect 35% CAGR $6.1 $13.9 $4.3 Storage 9% CAGR $4.2 $5.9 $6.5 CY23 CY28 prior CY28 update Compute is 29% larger, interconnect is 37% larger Source: 650
Slide 17: Marvell data center TAM
Marvell data center TAM $94B Accelerated $55.4 custom compute 35% 53% CAGR CAGR $13.2 Switching 17% CAGR $21B $6.6 $19.0 Interconnect 35% CAGR $6.1 $4.3 Storage 9% CAGR $4.2 $6.5 CY23 CY28 Source: 650 Group, CignalAI, Dell’Oro, LightCounting, and Marvell estimates © 2025 Marvell. All righ ts reserve
Slide 18: Marvell data center TAM
Marvell data center TAM $94B Accelerated $55.4 custom compute 53% CAGR $13.2 $21B $6.6 $19.0 $6.1 $4.3 $4.2 $6.5 CY23 CY28 Source: 650 Group, CignalAI, Dell’Oro, LightCounting, and Marvell estimates © 2025 Marvell. All righ ts reserved. 18
Slide 19: Accelerated custom compute TAM = XPU
Accelerated custom compute TAM = XPU XPUs Custom XPU Expanding opportunity with custom XPU attach © 2025 Marvell. All righ ts reserved. 19
Slide 20: Accelerated custom compute TAM = XPU + XPU attach
Accelerated custom compute TAM = XPU + XPU attach Networking Co-processor Memory XPUs Custom XPU Custom XPU attach Scale-up fabric Network interfaces, scale-up fabrics, security and host management co-processors, memory poolers Networking and expanders, etc. Expanding opportunity with custom XPU att
Slide 21: XPU attach becoming increasing portion of custom TAM
XPU attach becoming increasing portion of custom TAM $55.4B Custom XPU attach $14.6 90% CAGR 53% CAGR Custom XPU $40.8 47% CAGR $6.6B $0.6 $6.0 CY23 CY28 Source: 650 Group, Dell’Oro, and Marvell estimates © 2025 Marvell. All righ ts reserved. 21
Slide 22: Expanding multi-generational relationships
Expanding multi-generational relationships 12 6 18 Top 4 U.S. hyperscalers Emerging hyperscalers Accelerated custom Custom XPU Custom XPU Custom XPU Custom XPU sockets attach sockets sockets attach sockets compute sockets 3 9 2 4 © 2025 Marvell. All righ ts reserved. 22
Slide 23: Custom opportunity explosion
Custom opportunity explosion PIPELINE Opportunities 1/3 custom XPU 2/3 custom XPU attach >50 >10 $75B Each XPU Opportunities Customers Lifetime revenue Multi-$B lifetime 18 - 24 months Each XPU attach Several-$100M lifetime 2 - 4 years © 2025 Marvell. All righ ts reserved. 23
Slide 24: Why we win: differentiating with full-service custom
Why we win: differentiating with full-service custom System Design IP Silicon Packaging Manufacturing architecture services and logistics © 2025 Marvell. All righ ts reserved. 24
Slide 25: Leading-edge technology drives multi-gen wins
Leading-edge technology drives multi-gen wins Process IP Packaging OFC 2025 demo 2nm 16Å 14Å Nanometers World’s first 448G electrical Advanced to angstroms and optical SerDes packaging © 2025 Marvell. All righ ts reserved. 25
Slide 26: EDA in the cloud; Custom and networking silicon
EDA in the cloud Custom and networking silicon © 2025 Marvell. All righ ts reserved. 26
Slide 27: AWS collaboration quote
EDA in the cloud Custom and networking silicon “ Building a cost and power efficient cloud at the scale that only AWS can deliver begins with leading-edge semiconductors designed to meet the demanding infrastructure needs of our customers. Our expanded collaboration with Marvell enables us to deploy
Slide 28: Rani Borkar, Microsoft Azure (video)
Rani Borkar Corporate Vice President, Azure Hardware Systems and Infrastructure, Microsoft Video content © 2025 Marvell. All righ ts reserved. 28
Slide 29: Marvell's data center revenue
Marvell’s data center revenue $4.2B Future >50% custom Cloud AI ~$3.7B Q4 FY25 >25% custom On-prem ~$0.5B FY25 © 2025 Marvell. All righ ts reserved. 29
Slide 30: Driving to 20% share in custom compute and attach
Driving to 20% share in custom compute and attach Market share target 20% $55.4B Custom XPU attach $14.6 90% CAGR 53% CAGR Custom XPU $40.8 47% CAGR Market share <5% $6.6B $0.6 $6.0 CY23 CY28 Source: 650 Group, Dell’Oro, and Marvell estimates © 2025 Marvell. All righ ts reserved. 30
Slide 31: On track for 20% share in overall data center
On track for 20% share in overall data center $94B Custom XPU attach $14.6 90% CAGR $55.4 Custom XPU $40.8 47% CAGR $21B $13.2 Switching 17% CAGR $0.6 $6.0 $19.0 Interconnect 35% CAGR $6.1 $4.3 $4.2 $6.5 Storage 9% CAGR CY23 CY28 Source: 650 Group, CignalAI, Dell’Oro, LightCounting, and Marvell esti
Slide 32: On track for 20% share in overall data center
On track for 20% share in overall data center Market share target 20% $94B Custom XPU attach $14.6 90% CAGR Market ~13% $55.4 Custom XPU ~10% share $40.8 47% CAGR $33B $21B $13.2 Switching 17% CAGR $19.0 Interconnect 35% CAGR $6.5 Storage 9% CAGR CY23 CY24 CY28 Market share based on Marvell fiscal y
Slide 33: Larger TAM, more sockets, more customers
Larger TAM $75B $94B New markets Custom XPU Custom XPU attach Increasing share ~10% ~13% ... 20% More sockets won 3 18 More customers 4 >10 >50 opportunities $75B © 2025 Marvell. All righ ts reserved. 33
Slide 34: © 2025 Marvell. All righ ts reserved.
© 2025 Marvell. All righ ts reserved. 34
Slide 35: Chris Koopmans
Chris Koopmans Chief Operating Officer
Slide 36: Data center CAPEX to reach $1 trillion by 2028
Data center CAPEX to $1,022B reach $1 trillion by 2028 20% CAGR $593B $435B STARGATE $260B CY23 CY24 CY25 CY28 Source: Company public information, Dell’Oro © 2025 Marvell. All righ ts reserved. 36
Slide 37: 2028 data center infrastructure market
2028 data center infrastructure market Data center Equipment CAPEX Semiconductor Accelerated compute CAPEX (excluding physical infrastructure) TAM TAM $1,022B $825B $494B $349B Source: 650 Group, CignalAI, Dell’Oro, LightCounting, and Marvell estimates © 2025 Marvell. All righ ts reserved. 37
Slide 38: Breaking down accelerated computing TAM
Breaking down accelerated computing TAM Accelerated compute $349B $349B >2X $128 HBM attach $172B $58 XPU attach $163 XPU CY28 prior CY28 update CY28 Source: 650 Group, Dell’Oro, and Marvell estimates © 2025 Marvell. All righ ts reserved. 38
Slide 39: Breaking down accelerated computing TAM
Breaking down accelerated computing TAM Accelerated compute $349B HBM attach >2X HBM attach $172B $58 XPU attach $221B $163 XPU CY28 prior CY28 update CY28 Source: 650 Group, Dell’Oro, and Marvell estimates © 2025 Marvell. All righ ts reserved. 39
Slide 40: Custom silicon on track for 25% share of market by 2028
Custom silicon on track for 25% share of market by 2028 Accelerated compute Custom accelerated compute $221B $58 XPU attach 25% $55.4B $14.6 Custom XPU attach $163 XPU $40.8 Custom XPU CY28 update CY28 Source: 650 Group, Dell’Oro, and Marvell estimates © 2025 Marvell. All righ ts reserved. 40
Slide 41: Marvell custom silicon TAM
Marvell custom silicon TAM Marvell TAM $55.4B Custom XPU attach $14.6 90% CAGR 53% CAGR Custom XPU $40.8 47% CAGR $6.6B $0.6 $6.0 CY23 CY28 Source: 650 Group, Dell’Oro, and Marvell estimates © 2025 Marvell. All righ ts reserved. 41
Slide 42: Why custom? Diversity drives specialization, which drives customization
Why Diversity drives specialization, custom? which drives customization © 2025 Marvell. All righ ts reserved. 42
Slide 43: Race to the million-XPU cluster
Race to the million-XPU cluster speeding up xAI 1M XPUs Meta 200K XPUs Microsoft 100K 2025 XPUs Microsoft 14K 2024 10K XPUs 2023 XPUs 2020 © 2025 Marvell. All righ ts reserved. 43
Slide 44: Model innovation continues
Model innovation continues Large language model Reasoning model Content Live Search Code Complex Puzzle writing chatbots Analyze writing math solving Conclude Rise of inference-optimized infrastructure © 2025 Marvell. All righ ts reserved. 44
Slide 45: One size does not fit all
One size does not fit all Training Chain of thought Inference inference As AI workloads diversify, so must the infrastructure © 2025 Marvell. All righ ts reserved. 45
Slide 46: Diversification creates more opportunities
Diversification creates more opportunities © 2025 Marvell. All righ ts reserved. 46
Slide 47: Specialization drives diversity of compute core design
Specialization drives diversity of compute core design Inside the XPU Multiple points of optimization On-chip SRAM Core architectures Compute cores # cores Level of precision Interfaces Ratio of cores to memory Programmable, powerful, purpose-built © 2025 Marvell. All righ ts reserved. 47
Slide 48: And diversity of memory, packaging, connectivity
And diversity of memory, packaging, connectivity HBM HBM HBM HBM HBM HBM Interfaces Interfaces XPU XPU HBM HBM HBM HBM HBM HBM Beyond one chip, advanced packaging powers scale © 2025 Marvell. All righ ts reserved. 48
Slide 49: And diversity of the entire scaled-up platform design
And diversity of the entire scaled-up platform design Dual AI rack Optimized infrastructure for specific workloads © 2025 Marvell. All righ ts reserved. 49
Slide 50: AI infrastructure platform options
AI infrastructure platform options NVLink Fusion UALink announced May 18 announced June 11 XPU Custom Custom Custom Custom XPU General-purpose Third-party Standards- Full-custom attach platform platform based platform platform © 2025 Marvell. All righ ts reserved. 50
Slide 51: AI infrastructure platform options
AI infrastructure platform options NVLink Fusion UALink announced May 18 announced June 11 XPU Custom Custom Custom Custom XPU General-purpose Third-party Standards- Full-custom attach platform platform based platform platform Increasing custom XPU attach © 2025 Marvell. All righ ts reserved. 51
Slide 52: Growing TAM supports further pipeline expansion
Growing TAM supports further pipeline expansion $55.4B Custom XPU attach 90% CAGR $14.6 18 current sockets Custom XPU targeting 20% share 47% CAGR $40.8 >50 opportunities driving $75B CY28 Source: 650 Group, Dell’Oro, and Marvell estimates © 2025 Marvell. All righ ts reserved. 52
Slide 53: © 2025 Marvell. All righ ts reserved.
© 2025 Marvell. All righ ts reserved. 53
Slide 54: Nick Kucharewski
Nick Kucharewski SVP and GM, Cloud Platform
Slide 55: Marvell Custom Cloud Solutions
Marvell Custom Cloud Solutions 30 years of experience First-time-right silicon design Comprehensive portfolio Silicon-proven core enabling IP Full-lifecycle partnership Definition through deployment © 2025 Marvell. All righ ts reserved. 55
Slide 56: Choosing a custom silicon partner
Choosing a custom silicon partner © 2025 Marvell. All righ ts reserved. 56
Slide 57: Pace of innovation in AI cloud infrastructure
Pace of innovation in AI cloud infrastructure New key enabling technologies every year … applications demand system innovation every < 2 years … a 1-day delay means millions $ in lost revenue © 2025 Marvell. All righ ts reserved. 57
Slide 58: Full-service custom
Full-service custom System architecture Design IP Packaging Silicon services Manufacturing and logistics Physical design services Silicon Manufacturing services and logistics Manufacturing Manufacturing and logistics © 2025 Marvell. All righ ts reserved. 58
Slide 59: Marvell: Full-Lifecycle Custom Cloud
Marvell: Full-Lifecycle Custom Cloud System Design IP Silicon Packaging Manufacturing architecture services and logistics Unique differentiated technology, not available on the open market © 2025 Marvell. All righ ts reserved. 59
Slide 60: Projects begin years ahead of time
Projects begin years ahead of time New technology development Incubation 2-4 years before project start Evaluation and assessment System Concept systems enable customer exploration architecture Cooperative system definition Iterate on power, performance, cost tradeoffs © 2025 Marvell. All righ ts re
Slide 61: Key enabling core tech
Key enabling core tech SerDes Die-to-die Compute Packet Compute cores processing fabric Marvell Multi-die Security Ethernet Packet Specialized MAC fabric SW/FW Design IP Optics Compress / Custom Dense Hardened decompress HBM SRAM Arm Ecosystem Start-ups © 2025 Marvell. All righ ts reserved. 61
Slide 62: Running ahead of the customer project
Running ahead of the customer 5nm 3nm 2nm 16/14Å project Process enablement IP Test Model EDA migration silicon creation toolflow Silicon services Design execution Logic Physical DFT Power Yield design design and DFM tuning enhancement © 2025 Marvell. All righ ts reserved. 62
Slide 63: The key to scaling beyond Moore's Law
The key to scaling beyond Moore’s Law Advanced Multi-die HBM substrate Marvell custom Marvell custom Leadership and TSMC CoWoS and JEDEC roadmap Packaging CPC CPO Co-packaged copper Co-packaged optics © 2025 Marvell. All righ ts reserved. 63
Slide 64: Delivering quality at massive scale
Delivering quality at massive scale Scale Leading fabless manufacturer Quality Billions of device-hours over multiple decades Manufacturing and logistics Readiness Operations engineering for volume delivery Product Test Quality Reliability engineering engineering assurance assessment © 2025 Marvell.
Slide 65: Full-service custom
Full-service custom System architecture Design IP Packaging Silicon services Manufacturing and logistics Physical design services Silicon Manufacturing services and logistics Manufacturing Manufacturing and logistics © 2025 Marvell. All righ ts reserved. 65
Slide 66: Running faster and faster
Running faster and faster ~2x every ~2 years Process technology 3nm, 2nm, 16/14Å… Die-to-die interconnect 16 Gbps, 32 Gbps, 64 Gbps… High-speed SerDes 224 Gbps, 448 Gbps… 10x every ~2 years Advanced packaging 2.5D, 3.5D, advanced… Networking protocols Ethernet, NVLink, UALink… Leading systems need a
Slide 67: Marvell Full-Lifecycle Custom Cloud
Marvell Full-Lifecycle Custom Cloud CPU Partnership for system design Accelerator Exclusive enabling technology Fabric Experience at volume scale Interconnect NIC Switch © 2025 Marvell. All righ ts reserved. 67
Slide 68: © 2025 Marvell. All righ ts reserved.
© 2025 Marvell. All righ ts reserved. 68
Slide 69: Sandeep Bharathi
Sandeep Bharathi Chief Development Officer
Slide 70: Technical presenters
Ken Chang Mark Kuemerle Radha Nagarajan Mayank Mayukh SVP, Analog and Mixed VP, Technology, SVP and CTO, Senior Distinguished Engineer, Signal Engineering Custom Cloud Solutions Optical Engineering Advanced Packaging
Slide 71: AI compute cycle accelerates
AI compute cycle accelerates General-purpose compute Accelerated infrastructure 2 years < 1 year AI compute doubling less than a year © 2025 Marvell. All righ ts reserved. 71
Slide 72: AI accelerates single-die to multi-die transition
AI accelerates single-die to multi-die transition >1T >500B 200B >200B 3D and multi-die integration >100B Transistors 20-50B 10B >1B >10M Monolithic integration Mass production 2000 2020 2030 Source: Adapted from TSMC slide from IEDM conference. © 2025 Marvell. All righ ts reserved. 72
Slide 73: AI accelerates single-die to multi-die transition
AI accelerates single-die to multi-die transition >1T >500B 200B >200B >100B Transistors 20-50B 10B >1B >10M 2000 2020 2030 Trillion+ transistors requires rack-scale integration Source: Adapted from TSMC slide from IEDM conference. © 2025 Marvell. All righ ts reserved. 73
Slide 74: Proven Marvell technology stack
Proven Marvell technology stack Process Design IP flow Package Multi-generational execution track record © 2025 Marvell. All righ ts reserved. 74
Slide 75: Process, IP, Design, Package
Process Design IP flow Package © 2025 Marvell. All righ ts reserved. 75
Slide 76: Process technology leadership
Process technology leadership A14 A16 Most advanced process nodes N2P Product shipped Product development N3P Test chip IP start Foundry process enabled N5P 3-4 years lead time Validated critical IP ahead of product development © 2025 Marvell. All righ ts reserved. 76
Slide 77: Marvell IP across process technologies
Marvell IP across process technologies CMOS Silicon germanium Foundries Silicon photonics Process-agnostic. Foundry-ready. Future-proof. © 2025 Marvell. All righ ts reserved. 77
Slide 78: Process, IP, Design, Package
Process Design IP flow Package © 2025 Marvell. All righ ts reserved. 78
Slide 79: Anatomy of a modern XPU and CPO
Anatomy of a modern CPO SerDes CPO SerDes XPU D2D Die-to-die D2D D2D HBM HBM Dense SRAM Dense D2D D2D HBM HBM SRAM Custom HBM Dense SRAM D2D D2D HBM HBM Custom SRAM D2D SerDes CPO CPO Silicon photonics Industry-leading customized IP portfolio © 2025 Marvell. All righ ts reserved. 79
Slide 80: Anatomy of a modern XPU: SerDes
Anatomy of a modern SerDes XPU Die-to-die Custom HBM Custom SRAM Silicon photonics © 2025 Marvell. All righ ts reserved. 80
Slide 81: Anatomy of a modern XPU: advanced packaging
Anatomy of Advanced a modern packaging SerDes XPU Die-to-die Custom HBM Custom SRAM Silicon photonics © 2025 Marvell. All righ ts reserved. 81
Slide 82: Modern XPU and CPO, XPU attach
Modern XPU and CPO SerDes CPO SerDes XPU attach D2D D2D D2D Dense SRAM D2D D2D HBM HBM Dense Dense SRAM SRAM SerDes SerDes Dense D2D D2D D2D D2D Dense HBM SRAM HBM SRAM Dense Dense SRAM SRAM D2D D2D HBM HBM Dense SRAM D2D D2D D2D SerDes SerDes CPO CPO © 2025 Marvell. All righ ts reserved. 82
Slide 83: Modern XPU and CPO, XPU attach
Modern XPU and CPO SerDes CPO SerDes XPU attach D2D D2D Dense SRAM D2D D2D Dense SRAM SerDes SerDes D2D D2D D2D D2D Dense SRAM Dense SRAM D2D D2D Dense SRAM D2D D2D SerDes SerDes CPO CPO Customization to achieve the highest performance per watt © 2025 Marvell. All righ ts reserved. 83
Slide 84: Why is SerDes so difficult?
Why is SerDes so difficult? Figures of merit Reach Power Bit Latency error rate Marvell has multi-generational SerDes leadership © 2025 Marvell. All righ ts reserved. 84
Slide 85: Marvell IP leadership
Marvell IP leadership SerDes Custom Co-packaged Advanced HBM optics packaging Die-to-die Custom Silicon SRAM photonics Focused investment enables first-to-market advantage © 2025 Marvell. All righ ts reserved. 85
Slide 86: © 2025 Marvell. All righ ts reserved.
© 2025 Marvell. All righ ts reserved. 86
Slide 87: Ken Chang
Ken Chang SVP, Analog and Mixed Signal Engineering
Slide 88: Marvell SerDes leadership in IEEE spotlight
Marvell SerDes leadership in IEEE spotlight SerDes line rate vs. year and technology 400 Marvell 3nm Key leadership metrics 200 4nm Line rate Lowest power (Gb/s) 5nm Highest reach 100 7nm Lowest BER Lowest area 50 2018 2020 2022 2024 2026 Marvell SerDes recognized by IEEE Source: ISSCC, VLSI, OFC, i
Slide 89: Marvell SerDes leadership in IEEE spotlight
Marvell SerDes leadership in IEEE spotlight ISSCC 2022 ISSCC 2024 VLSI 2024 ISSCC 2025 VLSI 2025 OFC 2025 Demo Electrical 5nm 5nm 3nm 5nm 3nm 3nm 112 G 112 G 112 G 224 G 128 G 224 G SerDes XSR LR XSR LR LR LR Optical 5nm 5nm 5nm 5nm 3nm 3nm 200 G/lane 100 G/lane 200 G/lane 100 G/lane 200 G/lane 400
Slide 90: Marvell 3nm 224Gbps SerDes at OFC
Marvell 3nm 224Gbps SerDes at OFC 2m cable, 50dB loss bump-to-bump Level 4 Level 3 Level 2 Level 1 Transmitter output: clean eye Receiver input: closed eye After receiver / DSP: open levels Enabling next-generation XPU platforms © 2025 Marvell. All righ ts reserved. 90
Slide 91: Marvell die-to-die (D2D)
Marvell die-to-die (D2D) Today Tomorrow Future 10-20 Tbps / mm 30+ Tbps / mm 50+ Tbps / mm ~ 0.3pJ/bit ~ 0.2pJ/bit <0.1pJ/bit Beachfront LR Chip A D2D D2D Chip B LR Interposer Package GL-102 package © 2025 Marvell. All righ ts reserved. 91
Slide 92: © 2025 Marvell. All righ ts reserved.
© 2025 Marvell. All righ ts reserved. 92
Slide 93: Mark Kuemerle
Mark Kuemerle VP, Technology, Custom Cloud Solutions
Slide 94: Custom dense SRAM
CPO CPO SerDes D2D D2D D2D HBM HBM Dense SRAM Dense D2D D2D HBM HBM Custom dense SRAM SRAM Dense SRAM D2D D2D HBM HBM D2D SerDes CPO CPO On-chip embedded SRAM – customization is key © 2025 Marvell. All righ ts reserved. 94
Slide 95: Marvell custom SRAM
Marvell custom SRAM Key metrics for embedded memories Bandwidth / mm2 of memory options Marvell vs. industry 17x Marvell Area at same bandwidth 50% lower Standby power 66% lower Best available SRAM HBM4E Bandwidth Bandwidth / mm 2 at same area 17x higher Comparison of 1 Mb instance of third-party de
Slide 96: Custom HBM
CPO CPO SerDes D2D D2D D2D HBM HBM Dense SRAM Dense D2D D2D Custom HBM HBM HBM SRAM Dense SRAM D2D D2D HBM HBM D2D SerDes CPO CPO Custom HBM – high capacity with minimal overhead © 2025 Marvell. All righ ts reserved. 96
Slide 97: Enhancing XPUs with custom HBM architecture
Enhancing XPUs with custom HBM architecture Standard HBM Marvell Custom HBM No chiplets With I/O chiplets Compute Compute More area area area Standard HBM XPU Custom HBM XPU ▪ 1X useful compute area ▪ 1.7X useful compute area ▪ No compute area on HBM ▪ More compute area on HBM ▪ 1X power ▪ 75% lower
Slide 98: Package-integrated voltage regulation (PIVR)
Package-integrated voltage regulation (PIVR) 60% lower power noise Marvell PIVR Standard practice Typical PIVR accelerator on underside 85% lower IR power 15% lower total product power © 2025 Marvell. All righ ts reserved. 98
Slide 99: © 2025 Marvell. All righ ts reserved.
© 2025 Marvell. All righ ts reserved. 99
Slide 100: Radha Nagarajan
Radha Nagarajan SVP and CTO, Optical Engineering
Slide 101: Silicon photonics is critical for co-packaged optics
Silicon photonics is critical for co-packaged optics ▪ Optical system-on-chip ▪ High speed, long reach ▪ High volume CMOS fabs ▪ Complex electronics and photonics integration Highly integrated light engines for all interconnects © 2025 Marvell. All righ ts reserved. 101
Slide 102: Marvell silicon photonics at scale
Marvell silicon photonics at scale 100G 400G 800G 1.6T Field-proven Shipping Sampling Development 2017 2020 2023 2026 Multiple generations of field-deployed silicon photonics © 2025 Marvell. All righ ts reserved. 102
Slide 103: Marvell breaking 500 Gbps data rate barrier
Marvell breaking 500 Gbps data rate barrier Data rate and analog bandwidth (GHz) scaling 480 450 Gbps Gbps Optical demo Today OFC March 2025 enabled by Marvell high-speed analog components Electrical eye at 480 Gbps 224 Gbps Enables Application Single optical lane Lanes Format 112 1.6T ZR Between DC
Slide 104: Co-packaged optics to custom silicon interconnect
Co-packaged optics to custom silicon interconnect 3D integrated silicon photonics light engine Electronics Photonics Substrate Integration on reverse side 6.4T per engine 25.6T 4 engines 32 x 224G Custom silicon optical lanes interconnect High-density light engines Marvell high-density custom silico
Slide 105: © 2025 Marvell. All righ ts reserved.
© 2025 Marvell. All righ ts reserved. 105
Slide 106: Mayank Mayukh
Mayank Mayukh Senior Distinguished Engineer, Advanced Packaging
Slide 107: Marvell advanced packaging strategy
Marvell advanced packaging strategy Robust ecosystem for faster cadence between custom packaging generations Proprietary Fungible Custom technology building blocks packaging solution Materials, Scaling, optics, copper, + = process, design components Strategic Generational Faster partnership portfoli
Slide 108: Marvell advanced packaging portfolio
Marvell advanced packaging portfolio Road to packaging a trillion transistors together 2D package 2.5D package 3.5D package 4D package 4.5D package Integrated optics and copper Lid Silicon Stacked Advanced Silicon Substrate chiplets Interposers silicon chiplets substrates 1X 4X 8X 16X Yesterday Toda
Slide 109: Marvell advanced packaging toolbox
Marvell advanced packaging toolbox Fungible toolbox for generational portfolio Integrated optics and copper 3D-stacked silicon chiplets Bridge or RDL interposer Advanced substrates © 2025 Marvell. All righ ts reserved. 109
Slide 110: © 2025 Marvell. All righ ts reserved.
© 2025 Marvell. All righ ts reserved. 110
Slide 111: Will Chu
Will Chu SVP and GM, Custom Cloud Solutions
Slide 112: Compute ASIC + Custom Cloud Solutions
+ Compute ASIC Custom Cloud Solutions © 2025 Marvell. All righ ts reserved. 112
Slide 113: Strong design win momentum
Strong design win momentum 12 6 18 Top 4 U.S. hyperscalers Emerging hyperscalers Accelerated custom Custom XPU Custom XPU Custom XPU Custom XPU sockets attach sockets sockets attach sockets compute sockets 3 9 2 4 © 2025 Marvell. All righ ts reserved. 113
Slide 114: Typical system architecture
Typical system architecture Networking Co-processor Memory XPUs Custom XPU Scale-up fabric Custom XPU attach Networking © 2025 Marvell. All righ ts reserved. 114
Slide 115: Providing unique customer value: typical XPU
Providing unique customer value: typical XPU System Rack-scale enablement and optimization architecture Design IP Critical IPs SerDes Die-to-die Dense SRAM Hardened Arm Silicon Design-to-spec and co-development services Packaging Marvell custom and TSMC CoWoS Manufacturing Faster time to market and
Slide 116: Providing unique customer value: typical XPU attach
Providing unique customer value: typical XPU attach System Production FW/SW, boards, and ecosystem architecture Design IP Critical IPs Compress / Compute Security SerDes decompress fabric Silicon Design-to-spec integrating customer IP services © 2025 Marvell. All righ ts reserved. 116
Slide 117: Unique value across a single complete program
Unique value across a single complete program System IP development Execution Qualification Ship architecture Invest ahead Co-development Full ownership end-to-end Unmatched combination of technology, expertise and scale © 2025 Marvell. All righ ts reserved. 117
Slide 118: Unique value driving multi-generational partnerships
Unique value driving multi-generational partnerships System IP development (3nm) Execution Qualification Ship architecture System IP development (2nm) Execution Qualification Ship architecture System IP development (16Å) Execution Qualification Ship architecture Concurrent engagement enables a new c
Slide 119: Investing ahead in breakthrough technologies
Investing ahead in breakthrough technologies Marvell Introduces Optimized Marvell Develops Industry’s First 2nm Integrated Power Solutions Custom SRAM for Next-Generation to Boost Performance, Efficiency, AI Infrastructure Silicon and ROI of Accelerated Infrastructure June 17, 2025 June 17, 2025 Mar
Slide 120: Rapidly expanding pipeline
Rapidly expanding pipeline >50 1/3 custom XPU Opportunities 2/3 custom XPU attach Engaged in every opportunity and well-positioned for growth © 2025 Marvell. All righ ts reserved. 120
Slide 121: © 2025 Marvell. All righ ts reserved.
© 2025 Marvell. All righ ts reserved. 121
Slide 122: © 2025 Marvell. All righ ts reserved.
© 2025 Marvell. All righ ts reserved. 122
Slide 123: © 2025 Marvell. All righ ts reserved.
© 2025 Marvell. All righ ts reserved. 123
Slide 124: Custom AI Investor Event
=| MARVELL’ Custom AI Investor Event June 17, 2025