Arteris, Inc. · NASDAQ:AIP
Arteris — Chiplet Summit '24 (February 2024)
28 slides from Arteris's conference presentation, Feb 7, 2024
Slide 1: Efficient Transport in Chiplet-Based AI/ML Applications
Efficient Transport in Chiplet-Based AI/ML Applications Chiplet Summit ’24 Frank Schirrmeister, VP Solutions Guillaume Boillet, Sr. Director and Business Development Strategic Marketing February 7, 2024 1 © 2024 Arteris, Inc.
Slide 2: Arteris – A Leading SoC System IP Company
Arteris – A Leading SoC System IP Company Global customer base deploying Arteris interconnect IP and SoC Integration Software Silicon-proven IP used in ~3.5 billion+ SoCs shipped to date Diversified Customer Base Subset of Publicly Disclosed Customers 200+ customers and 725+ SoC design starts to
Slide 3: Embracing the Chiplet Revolution: Why and for Whom?
Embracing the Chiplet Revolution: Why and for Whom? Exploring the Four Key Drivers and Adoption Across Five Verticals Cloud AI Personal (Training & Assistant ADAS Inference) Scalability Technology scaling, chiplet grids, overcome reticle limits, Size of Opportunity I/O bandwidth Timeline of Adopti
Slide 4: AI/ML Happens Everywhere
AI/ML Happens Everywhere Device Far Near Cloud Data Edge Edge Edge Center Sensor Edge Sensors / Cloud Far Edge Near Edge Devices Datacenter <1 ms 0.1 - 1 ms 1-10 ms >10 ms <10 m 10 m - 1 km 1-10 km 10+ km Reduce latency, Focus on inferencing Training and inferencing, bandwidth usage, protect Lightwe
Slide 5: AI Chip Disaggregation
AI Chip Disaggregation Mem Ctrl Mem Ctrl Mem Ctrl Mem Ctrl Basic Components Mem Ctrl Mem Ctrl Tensor Cores or Arithmetic Units – Specialized in handling matrix multiplications and accumulations at high speeds Mem Ctrl Mem Ctrl Memory – On-chip caches, buffers, and off-chip memory interfaces – SR
Slide 6: From Proprietary to Ecosystem
From Proprietary to Ecosystem Proprietary Locally Controlled Open Marketplace Accelerators AI-Enabled & AI-enabled Systems Systems MEM MEM MEM Die B Die B Die A Die B Die A Die B Die A Die B Die A Die B D2D D2D D2D D2D D2D D2D D2D D2D D2D D2D D2D D2D Die X Die X Die X (NoC) (NoC) (NoC) Die C Die C D
Slide 7: Chiplet Routing Topologies
Chiplet Routing Topologies Non-Coherent Systems One-to-One Direct Routing Static Indirect Routing Dynamic Indirect Routing Non-Coherent Accelerator Die A Die A Die B Die A Die A Die A Die A Die A D2D D2D D2D D2D D2D D2D D2D D2D D2D D2D D2D D2D D2D D2D D2D Disaggregated D2D D2D D2D Die A Die B D2D D2
Slide 8: The Multi-Die Systems Landscape
The Multi-Die Systems Landscape Layered Architecture Chiplet Need for coherency, direct vs. indirect routing, single vs. Topology multi-vendor... Protocol Layer PCIe, CHI, AXI, CXL, CCIX, Proprietary,... Link Layer Packetization via AMBA CXS, UCIe FDI, Proprietary,... Physical Layer PCIe, UCIe, Bo
Slide 9: Various Implementations & Applicability to AI Systems
Various Implementations & Applicability to AI Systems Non-Coherent Coherent AI-Enabled Accelerators Accelerators Systems Non-Coherent Multi-Die Coherent NoC Connection to Coherent NoC Across Interoperable Coherent NoC Interoperable Asymmetric Connectivity 3rd-Party Chiplets Multiple Dies Connection
Slide 10: Multi-Die Links for AI Accelerators Scalability
Multi-Die Links for AI Accelerators Scalability Non-Coherent Link Die 1 Physical Die 2 channel UCIe UCIe BoW BoW AXI Link XSR XSR Link AXI FlexNoC Pack Layer PHY PHY Layer Unpack FlexNoC Protocol to Data-link CRC Check Stream to stream Retry Buffer Data-link Retry protocol Coherent Link Die 1 Physic
Slide 11: Network-on-Chip (NoC)
Network-on-Chip (NoC) Interconnect IP is Critical to Every SoC to Enable Next-Generation Technologies Smaller Lower Power Faster Frequency Shorter, Predictable Rapid Timing Automated Easy Die Area Consumption Lower Latency Schedules Closure Estimation Verification Configuration CPU Subsystem Domain-
Slide 12: Specific AI/ML Requirements for Network-on-Chip Design
Specific AI/ML Requirements for Network-on-Chip Design 12 © 2024 Arteris, Inc.
Slide 13: AI Chip Anatomy
AI Chip Anatomy Basic Components Tensor Cores or Arithmetic Units – Specialized in handling matrix multiplications and accumulations at high speeds Memory – On-chip caches, buffers, and off-chip memory interfaces – SRAM for weights, biases, and intermediate activation maps Mem Ctrl Mem Ctrl – Pr
Slide 14: Memory Latency is Critical: Xeon Example
Memory Latency is Critical: Xeon Example 14 © 2024 Arteris, Inc. Source: Arteris, http://www.qdpma.com/ServerSystems/MemLat2018.html
Slide 15: The Common Problem: Data Storage and Transport
The Common Problem: Data Storage and Transport Hitting the Memory Wall Memory and Data Transport Issues Growing SoC Complexity – CPU, GPU Performance and Memory DRAM accesses kill performance and power consumption SoC architects must balance local data reuse vs. sharing within the chip and into
Slide 16: Example SoC AI DNN Requirements: Automotive Vision
Example System-on-Chip AI DNN Requirements: Automotive Vision Performance AND Low Power Functional Safety 16 © 2024 Arteris, Inc. Source: Toshiba, DNN-Accelerated Multi-core SoC for Automotive Applications, MPSOC 2019
Slide 17: Example: Arteris IP in Toshiba ADAS SoC
Example: Arteris IP in Toshiba ADAS SoC NoC interconnect IP enables low power, high performance and safety PI Domain ( ASIL C ) Cache Coherent Interconnect: Ncore Non-coherent Interconnect: FlexNoC with Resilience Package Ncore Ncore FlexNoC FlexNoC – 8 NoC instances and all of them use Resilien
Slide 18: Example Results - Toshiba
Example Results - Toshiba Performance AND Low Power Safety 18 © 2024 Arteris, Inc. Source: Toshiba, DNN-Accelerated Multi-core SoC for Automotive Applications, MPSOC 2019
Slide 19: Example: Ncore Cache Coherent Interconnect IP
Example: Ncore Cache Coherent Interconnect IP Multi-protocol AMBA CHI and ACE cache coherent interconnect Scalable and Flexible – Ncore Cache Coherent Interconnect IP supports multiple coherent agents, allowing for the design of highly flexible SoC platforms tailored to meet changing product requi
Slide 20: Overcoming Large Chip Hurdles
Overcoming Large Chip Hurdles Overcoming Large Chip Hurdles Efficiently Managing Bandwidth Source synchronous communications and virtual channels avoid Integration with HBM2 multichannel memory controllers timing closure issues by managing long cross-chip paths 8- or 16-channel interleaving effect
Slide 21: Mesh Interconnect for AI/ML
Mesh Interconnect for AI/ML Large-scale topologies for deep neural network (DNN) and machine learning(ML) Advanced mesh-based interconnect generation from JSON file or from the GUI Expanded number of NoC Initiators and Targets Up to 1024bit wide data connections Broadcast links, virtual chan
Slide 22: Resilience / Safety Requirements
Resilience / Safety Requirements CPU duplication and memory protection logic are no longer sufficient to address all the metrics required to meet the more stringent ISO 26262 ASIL and IEC 61508 SIL levels. Data traffic must now be protected throughout the chip floorplan. ISO 26262 ASIL D certifiab
Slide 23: Architecture Analysis and Coherency
Architecture Analysis and Coherency … System … System Accelerators Accelerators Components Components … System high performance NoC CPU cluster CPU cluster Accelerator NoC Coherent interconnect System Architecture Memory NoC Analysis DRAM … DRAM Memory channel channel targets All interconnect/NoC co
Slide 24: Summary Hierarchical Setup
Summary Hierarchical Setup Arteris IP Imported into Synopsys Platform Architect 3 1 Configuration interface Ncore3 verilated model Ncore3 TLM FlexNoC TLM 4 2 Bus Library Framework Traffic Analysis CodaCache imported as verilated model 24 © 2024 Arteris, Inc. Source: Arteris FlexNoC, Synopsys Platfor
Slide 25: Arteris Enables AI/ML Everywhere!
Arteris Enables AI/ML Everywhere! Publicly Announced Customers Device Far Near Cloud Data Edge Edge Edge Center Sensor Edge <10 m 10 m - 1 km 1-10 km 10+ km Sensors/Devices Far Edge Near Edge Cloud Data Center Autochips Aeva Baidu Black Sesame Axelera Biren BOS Semi Canaan Bitmain Cambricon Blue Oce
Slide 26: Recent Customer Momentum
Recent Customer Momentum Connectivity across the NR1 Telechips integrates Arteris Arteris collaborates with chip within the inference server IP for Automotive applications SiMa.ai to optimize ML SoC to efficiently meet high-density, including ADAS and MCUs, implementation with efficient low-latency
Slide 27: Recent Customer Momentum
Recent Customer Momentum Tenstorrent selected Arteris Arteris IP licensed by Axelera Arteris IP selected by for AI high-performance AI to accelerate computer ASICLAND for automotive, computing and datacenter vision at the edge enabling AI enterprise and AI edge RISC-V chiplets to enable Axelera AI e
Slide 28: Thank you
Thank you Contact us for more information frank.schirrmeister@arteris.com guillaume.boillet@arteris.com Arteris, Inc. All rights reserved worldwide. Arteris, Arteris IP, the Arteris IP logo, and the other Arteris marks found at https://www.arteris.com/trademarks are trademarks or registered trademar