Keysight Technologies Inc. · NYSE:KEYS
Keysight Technologies — Technical Presentation (2025)
49 slides from Keysight Technologies's technical presentation, Feb 27, 2025
Slide 1: The Road to PCIe 7.0: Advanced Testing Challenges at 64 GBaud PAM4
The Road to PCIe 7.0: Advanced Testing Challenges at 64 GBaud PAM4 Rick Eads, Pegah Alavi, Randy Garrett Solution Planners 1
Slide 2: Agenda
Agenda • PCIe Development and Timeline • PCIe 7.0 Significant Features • PCIe 7.0 PAM4 Measurement Challenges • PAM4 Simulation Insights and Techniques • PCIe 6.0 Protocol Test Tools 2
Slide 3: PCI Express Bandwidth Growth
PCI Express Bandwidth Growth Keeping the Pace of Innovation Going 3
Slide 4: PCI Express Evolution – Pathway to 128GBit
PCI Express Evolution – Pathway to 128GBit PCIe Innovation accelerating at a rapid pace Cadence between PCIe Generations Reduced by 1/3 • Increased speed means Increased complexity • New measurement challenges are here 2024-2027 PCIe 7.0 (128 GT/s) • No sign of slowing… 2022 2019 PCIe 6.0 (64 GT/s)
Slide 5: Complete PCIe Solution Today
Complete PCIe® Solution Today NEW! Physical Layer- Physical Layer- Physical Layer- Physical Layer- Protocol Layer Test System Simulation Interconnect Design Transmitter Test Receiver Test 5 ADS Design Software ADS Design Software M8040A/M8050A High P5573A PCIe 6.0 Exerciser UXR-Series Real-Time Perf
Slide 6: PCIe 7.0 Specification
PCIe 7.0 Specification Data Rate, Signaling, BER, and Channel PCIe 7.0 Category Objective Data Rate 128 GT/s, PAM4 (2x Gen6) Forward Error Correction Maximum First Bit Error Rate (FBER) of 1e-6 (not accounting for burst errors) Latency <1ns adder for Transmitter + Receiver over 64GT/s 4”-14” system
Slide 7: PCIe 7.0 128 GT/s Technology
PCIe 7.0 128 GT/s Technology Transmitter Pathfinding PCIe 7.0 ASIC/IC Custom Breakout Board CTLE Breakout Channel Compensation 7
Slide 8: Linear Equalization Differences between 128GT/s and 64GT/s
Linear Equalization Differences between 128GT/s and 64GT/s CTLE Equalization for 64GT/s (Gen6) CTLE Equalization for 128GT/s (Gen7) 8
Slide 9: How Much Bandwidth is needed for 128GT/s TX Measurements?
How Much Bandwidth is needed for 128GT/s TX Measurements? What we know for PCIe 7.0 • Nyquist doubles to 32GHz • Harmonics at 64GHz and 96GHz • Bessel Thomson Filter Bandwidth is calculated at -9dB point • 64GBaud/2*1.5=48GHz BT at -3dB point and 73GHz at -9dB. • Most critical measurement is BERT TX
Slide 10: How Much Bandwidth is needed for 128GT/s TX Measurements?
How Much Bandwidth is needed for 128GT/s TX Measurements? LAB Data for PCIe 7 • Nyquist doubles to 32GHz • Harmonics at 64GHz and 96GHz • Bessel Thomson Filter Bandwidth is calculated at -9dB point • 64GBaud/2*1.5=48GHz BT at -3dB point and 73GHz at -9dB. Spectral content appears negligible beyond 6
Slide 11: 64GBaud PAM4 TX Measurements
64GBaud PAM4 TX Measurements Advancing PCIe Technology to the next Level of Performance ▪ Signal to Noise and Distortion Ratio Signal Measurement Improvements for 32GBaud ▪ Pmax ▪ Pmax2 is replaced with the sum of squares of linear fit pulse response p(k) and P0(k) for both even symbols and odd symb
Slide 12: PCIe 7.0 SNDR Definition
PCIe 7.0 SNDR Definition Lab Measurements of 128GT/s Silicon • PE and PO are the even and odd linear fit pulse responses (LFPRs) • σe= standard deviation of the fit error e(k) • σn= avg noise of all four PAM4 voltage levels • σn= ¼ (σ1+ σ2+ σ3+ σ4) 12
Slide 13: Transmitter Linearity
Transmitter Linearity Measured RLM Calculation of RLM V3 • Verify linear spacing of the PAM4 levels • Uses PCIe 6.0 64 GT/s compliance pattern V2 Vmid • Determining VL is based on Linear Fit Pulse V1 Response (multi-pulse ECR*) V0 RLM >= 95.0% With the multiple, linear fit pulse response based RLM t
Slide 14: Updated Jitter Patterns for 128GT/s Jitter Measurement
Updated Jitter Patterns for 128GT/s Jitter Measurement LSTP0 (01b & 10b) LSTP2 (00b & 01b) LSTP3 (00b & 10b) LSTP4 (10b & 11b) LSTP1 (01b & 11b) • 52UI Jitter Pattern @64GBaud 14
Slide 15: 64GBaud Channel Targets
64GBaud Channel Targets • Two types of PCIe Channel Targets • Client: ~25cm-35cm with 1 connector • Server: ~50cm with 2 connectors (2 retimers allowed) Server Use • Concerns at 64GBaud CEM Connector Case Riser Client • Insertion loss at 32GHz will benefit from new materials Use Case AIC • CEM conne
Slide 16: Establishing a 128GT/s Reference Receiver
Establishing a 128GT/s Reference Receiver • Reference Package Models for 128GT/s • Requires improvements in insertion loss, return loss, and crosstalk are assumed in the reference package models used for channel compliance and also stressed receiver test calibration. • Reference Receiver Elements •
Slide 17: PCI Express v6.0 Solution Testing
PCI Express v6.0 Solution Testing M8040A 64 GbaudHigh-Performance NRZ PAM4 BERT M8040A High-Performance BERT 64 Gbaud NRZ & PAM4 A picture containing indoor, black, computer, sitting Description automatically generated Recommended Software: • D9020ASIA Advanced Signal Integrity Software (EQ, Infinii
Slide 18: PCI Express v7.0 Solution Testing
PCI Express v7.0 Solution Testing M8050A 120 Gbaud High-Performance NRZ PAM4 BERT M8050A High-Performance BERT 120 Gbaud NRZ & PAM4 Recommended Software: • D9020ASIA Advanced Signal Integrity Software (EQ, InfiniiSimAdv, Crosstalk) • D9020JITA EZJIT Complete • D9010PAMA PAM-N Analysis • M8070B BERT
Slide 19: PCIe 6.0 & 7.0: PAM4 Simulation Insights and Techniques
PCIe 6.0 & 7.0: PAM4 Simulation Insights and Techniques 19
Slide 20: PAM4 Simulation Insights for PCIe 7.0 and PCIe 6.0
PAM4 Simulation Insights for PCIe 7.0 and PCIe 6.0 • Multi-Level Signaling Challenges • PCIe 6.0 & PCIe 7.0: Designer’s need, Simulation must haves • PCIe 7.0 End to End Simulation • PCIe 6.0 End to End Simulation • IBIS-AMI model generation • Compliance from within ADS 20 20
Slide 21: PCIe: The Data Rate, The channel, The challenge!
PCIe: The Data Rate, The channel, The challenge! PCIe 6.0 (64 GT/s) 2021-2022 2024-2025 PCIe 7.0 (128 GT/s) 2019 2022 PCIe PCIe 5.0 (32GT/s) 6.0 (64 GT/s) 2019 2017 PCIe 5.0 (32 GT/s) PCIe 4.0 (16 GT/s) 2017 PCIe 4.0 (16 GT/s) 2010 2010 PCIe 3.0 (8 GT/s) PCIe 3.0 (8 GT/s) 2006 2006 PCIe 2.0 (5 GT/s)
Slide 22: Where are we going?
Where are we going? Level Up • Adoption of Multi-Level Signaling reduces the occupied Bandwidth/Bit by mapping >1 bit into a transmitted symbol. • Symbol Rate is Bit-Rate/Bits-per-Symbol • Nyquist frequency is similarly reduced © Keysight Technologies 2022 22
Slide 23: Multi-Level Challenges
Multi-Level Challenges MAKING IT ALL WORK • Some challenges of multi-level signaling: • The S/N is reduced as the number of Levels increases • Higher raw error rates => FEC • Multiple transitions between Levels will reduce Eye widths • Asymmetric Eyes • All Levels/Eyes should be treated equally • Le
Slide 24: Ensuring PAM Design Success
Ensuring PAM Design Success W H AT T O O L S D O D E S I G N E R S N E E D ? • Comprehensive Simulation Capability • SER (Up to millions per minute) • Eye measures • Bathtubs • Mask tests • Diagnostics for design development • Waveforms • Linearity • Skew • Jitter • Models • Channel, Pre and Post la
Slide 25: PCIe 7.0 Transmitter equalization
PCIe 7.0 Transmitter equalization 25
Slide 26: PCIe 7.0 Receiver equalization: CTLE
PCIe 7.0 Receiver equalization :CTLE 26
Slide 27: PCIe 7.0 Receiver Equalization: FFE+DFE
PCIe 7.0 Receiver Equalization: FFE+DFE 29 tap FFE: Single Tap DFE |d1/h0| < 0.5 27
Slide 28: PCIe 7.0 Receiver Equalization: CDR
PCIe 7.0 Receiver Equalization: CDR 2nd Order CDR 28
Slide 29: PCIe 7.0: End to End Simulation
PCIe 7.0: End to End Simulation Mask: Top eye: EH≥10mVpp; EW≥0.1 UI 30
Slide 30: PCIe 7.0: End to End Simulation
PCIe 7.0: End to End Simulation Mask: Top eye: EH≥10mVpp; EW≥0.1 UI 31
Slide 31: PCIe 7.0: End to End Simulation
PCIe 7.0: End to End Simulation Mask: Top eye: EH≥10mVpp; EW≥0.1 UI 32
Slide 32: PCIe 6.0: End to End Simulation
PCIe 6.0: End to End Simulation 33
Slide 33: Don't have an IBIS-AMI model? No problem!
Don’t have an IBIS-AMI model? No problem! PCIe IBIS-AMI Modeler You can build your own AMI models easily and quickly! PAM4 MODULATION AND WEIGHTED SUM OF DFE TAPS • Builds PCIe 6.0 PAM4 AMI Models for Tx and Rx • Supports weighted sum of DFE taps • Wizard driven model generation workflow PCIe AMI Mo
Slide 34: System Designer for PCIe (W3651B)
System Designer for PCIe® (W3651B) A smarter design workflow for PCIe® applications • Streamlined design and simulation workflow for PCIe® applications: both PAM4 & NRZ (PCIe 7.0, 6.0, 5.0, etc) • Supports multi-links and multi-lanes PCIe® system • PCIe_RootComplex, PCIe_EndPoint, PCIe_Repeater, PCI
Slide 35: Dedicated PCIe Simulator
Dedicated PCIe® Simulator in System Designer for PCIe® • Supported simulation modes • Bit-by-Bit • Statistical • Seasim Interface • S-Parameter • Unified simulator 37
Slide 36: Direct access to Seasim Interface
Direct access to Seasim Interface in System Designer for PCIe® Seasim location Seasim configuration 38
Slide 37: Simulation Solutions: Complete Design to Test Workflow
Simulation Solutions: Complete Design to Test Workflow Simulation Driven Virtual Compliance Test Device Test Pre-Silicon Physical Virtual Pre-Layout Virtual Post-Layout Compliance Compliance Compliance Compliance Testing Testing Testing Testing System Test Mfg, Assembly… Physical System Design: Syst
Slide 38: PCIe Compliance Solution
PCle Compliance Solution PCle Simulator PCle Simulator Number0/Bits=10000 ToleranceMode=Auto EnforcePassivity=yes Mode=Bit-by-bit Start=1.0 GHz Stop=10.0 GHz PCle-Setup Step=1.0 GHz PCle Setup PoieGeneration="5" UseCustomDataRate=no DataRate=16 IbisCornerVarForBatchsim="P ClelbisComeSweepVar" OpenSp
Slide 39: PCIe Compliance Test with Simulation-Driven Workflow
PCIe Compliance Test with Simulation-Driven Workflow PCIe Compliance Probe Select a probe for current test point, the probe will be displayed next to the test point and removed from the drop-down list Detect all available EyeDiff_Probe on schematics and list here S1000 HSD-4 Demystifying Compliance
Slide 40: Compliance Test Workflow Options
Compliance Test Workflow Options Live Signal • Set up configs and signal source from Infiniium (Live Mode) channels Waveform Result • Set up configs and load Generate Files Compliance App storage waveform files to Run tests Test (Offline and Compliance app manually Results Mode) analysis Simulation
Slide 41: Complete Keysight PCIe Solution Today
Complete Keysight PCIe® Solution Today Physical Layer- Physical Layer- Physical Layer- Physical Layer- Protocol Layer Test System Simulation Interconnect Design Transmitter Test Receiver Test 4 ADS Design Software ADS Design Software M8040A High Performance BERT P5551A PCIe 5.0 Exerciser 5 UXR-Serie
Slide 42: Advanced Test Challenges for PCIe 5.0 / 6.0 and CXL
Advanced Test Challenges for PCIe 5.0 / 6.0 and CXL PCIe 5.0 and CXL 2.0 • 32 GT/s NRZ (1 bit per clock) • First Bit Error Rate (FBER) 1e-12 • Variable size TLP packets PCIe 6.0 and CXL 3.0 • 64 GT/s PAM4 (2 bits per clock) • FBER 1e-06 • Forward Error Correction (FEC) Effective BER 1e-12 • Flow Con
Slide 43: Product Overview - PCIe 6.0 and CXL Protocol Hardware
Product Overview - PCIe 6.0 and CXL Protocol Hardware First CEM Card Analyzer Form Factor P5570A PCIe 6.0 Protocol Analyzer • PCIe 6.0, 64GT/s PAM4, and CXL • Traffic Capture and Decode (16GB memory) • Direct Plug-In with no additional cables • Protocol trace Capture: • Physical Layer (TS1/TS2/Order
Slide 44: PCIe 6.0 Analyzer Decoding: FLIT Viewer
PCIe 6.0 Analyzer Decoding: FLIT Viewer 48
Slide 45: Integrated Analyzer Interposer
Integrated Analyzer Interposer Signal Integrity is Critical for PAM-4 Protocol Decode Goal: Protocol analyzer is transparent to the system under test Solution: Having analyzer on same card as tap point allows similar signal strength and quality to be delivered to analyzer and connector, and greatly
Slide 46: Keysight PCIe Protocol Analyzer
Keysight PCIe Protocol Analyzer Measurement Setup for Through-Path: Signal Integrity Performance in the Frequency Domain Setup for reference measurement; 2x Breakout boards and P5563B Testbackplane Setup for Analyzer Through Path measurement: VNA port 1diff VNA port 2diff 50
Slide 47: Keysight PCIe Protocol Analyzer
Keysight PCIe Protocol Analyzer Through-Path: Signal Integrity Performance Frequency Domain Reference: Fixture1-TP-Fixture2 ANA in-between w/ optimized Settings DIFF: ~0.5dB @ 8GHz DIFF: ~0.75dB @ 16GHz DIFF: ~2dB @ 25GHz 51
Slide 48: Complete Keysight PCIe Solution Today – Booth 1039
Complete Keysight PCIe® Solution Today – Booth 1039 Physical Layer- Physical Layer- Physical Layer- Physical Layer- Protocol Layer Test System Simulation Interconnect Design Transmitter Test Receiver Test 5 ADS Design Software ADS Design Software M8040A High Performance BERT P5551A PCIe 5.0 Exercise
Slide 49: Keysight
MW KEYSIGHT
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