Slide 1: Rambus Investor Presentation
Rambus Investor Presentation Q3 2026
Slide 2: Safe Harbor for Forward-Looking Statements; Other Disclosures
Safe Harbor for Forward-Looking Statements; Other Disclosures This presentation contains forward-looking statements, including those relating to the Company’s expectations regarding business opportunities, the Company’s ability to deliver long-term profitable growth, industry growth rates, timing of
Slide 3: Record Revenue
Record Revenue $2.51 $708M Diluted Non-GAAP EPS 2025 Revenue Data Center & AI >75% of Chip and $348M Silicon IP Revenue 2025 Product Revenue $360M +25% 2025 Cash from Operations 5-YR CAGR Product Revenue Over 3 Decades San Jose HQ ~800 Employees Technology Leadership Global Footprint >70% in Enginee
Slide 4: Semiconductor Solutions Built on Innovation
Semiconductor Solutions Built on Innovation Rambus Offerings Markets Served Chips Memory Interface Product Sales Automotive Chips Silicon IP Data Center IP Licenses Government & Edge Interface IP Security IP Innovations Patent Licenses \ IoT Foundational R&D and IP 4
Slide 5: Amplified Opportunities in Data Center and AI
Amplified Opportunities in Data Center and AI Meeting memory performance Addressing bandwidth and Broadening adoption of requirements of growing capacity requirements with novel key technologies into AI workloads memory solutions adjacent markets Cache Increasing latency and capacity On chip Perform
Slide 6: Rambus Solutions for the Data Center
Rambus Solutions for the Data Center DDR5 RDIMM Server Motherboard AI Accelerator/GPU Card 2 1 3 4 Rambus Products: Chips 1 Memory Interface Chips: Registering Clock Driver, PMIC, SPD Hub, Temperature Sensor 2 Root of Trust Security IP with Quantum Safe Cryptography Silicon IP 3 HBM/GDDR/LPDDR Memor
Slide 7: Rambus Memory Interface Chips
DDR5 Server Chipset Rambus Memory Interface Chips Offering chipset solutions for all industry-standard DDR5 and LPDDR5/5X memory modules Expanding portfolio of new products: Complete Chipsets for: Industry-leading DDR5 RCDs • MRCD & MDB 12800 MT/s • RDIMM • CUDIMM • PMICs and Voltage Regulators • MR
Slide 8: Silicon IP Solutions for AI
Silicon IP Solutions for AI • Critical IP for accelerator, networking and storage chips: HBM, GDDR, LPDDR, PCIe, CXL, PQC, Root of Trust, IME/IDE, MACsec, IPsec and UET-TSS • Key Benefits • Delivers industry-leading bandwidth performance • Enables high-speed connectivity between devices Interface IP
Slide 9: Rambus Uniquely Positioned for Novel Memory Solutions
Rambus Uniquely Positioned for Novel Memory Solutions Industry leading performance to 12800 MT/s (MRDIMM) Industry Leadership and 9600 MT/s (RDIMM) for DDR5-based servers and PCs DDR5 Memory Interface Chipset HB M 4 E M e m or y S ub sy st em World-class expertise in memory interface and Core Expert
Slide 10: Product Leadership Driving Long-term Growth
Product Leadership Driving Long-term Growth DDR5 & LPDDR5/5X memory module chipsets delivering industry-leading performance z Critical interface IP for AI: 2020-2025 z HBM & GDDR controllers; PCIe controller, switch & retimer 25% Product Revenue Broadest portfolio of secure root of trust, protocol e
Slide 11: Financial Highlights
Financial Highlights Product Revenue* ($M) Pro Forma Operating Expenses ($M) 249 218 217 348 82 77 76 225 247 167 141 146 2023 2024 2025 2023 2024 2025 *Consisting Primarily of Memory Interface Chips R&D SG&A Cash from Operations ($M) & FCF per Share ($) Cash Equivalents & Return of Capital ($M) 400
Slide 12: Rambus Investment Summary
Rambus Investment Summary ➢ AI-driven data center growth expands long-term market opportunity ➢ Broad portfolio of high-performance chips and silicon IP enables critical performance improvements for AI and advanced workloads ➢ Innovation feeds sustained product leadership and strong patent portfolio
Slide 13: Detailed Financials
Detailed Financials Strong cash generation fuels growth initiatives and return of value to stockholders
Slide 14: Q2 2026 Non-GAAP Income Summary
Q2 2026 Non-GAAP Income Summary In Millions, except EPS Q2 2025 Q3 2025 Q4 2025 Q1 2026 Q2 2026 Revenue $172.2 $178.5 $190.2 $180.2 $207.4 Achieved record quarterly revenue Total Operating Costs and Continued investment to support core $93.2 $99.3 $103.2 $104.6 $113.7 Expenses (1) growth initiatives
Slide 15: Q2 2026 Balance Sheet Summary
Q2 2026 Balance Sheet Summary In Millions Q2 2025 Q3 2025 Q4 2025 Q1 2026 Q2 2026 Total Cash & $594.8 $673.3 $761.8 $786.1 $824.9 Driven by consistent cash from operations Marketable Securities Total Assets $1,467.8 $1,406.4 $1,529.5 $1,533.1 $1,612.3 Strong balance sheet and debt free Stockholders’
Slide 16: Reconciliation of GAAP to Non-GAAP Financial Measures
Reconciliation of GAAP to Non-GAAP Financial Measures Operating Income in Millions, except EPS Q2 2025 Q3 2025 Q4 2025 Q1 2026 Q2 2026 GAAP Operating Income $63 $63 $71 $62 $73 Adjustments: Stock-based compensation 14 14 14 11 16 Amortization of acquired intangible assets 2 2 2 2 2 Restructuring and
Slide 17: Reconciliation of GAAP to Non-GAAP Income Statement
Reconciliation of GAAP to Non-GAAP Income Statement GAAP Non-GAAP Delta In Millions, except EPS Actual Actual to Q2 2026 Q2 2026 GAAP Revenue $207.4 $207.4 $- Cost of revenue 42.0 40.2 (1.8) Research and development 51.1 45.0 (6.1) Sales, general and administrative 38.3 28.5 (9.7) Restructuring char
Slide 18: Revenue and Licensing Billings
Revenue and Licensing Billings ASC 606 ASC 606 In Millions Q1 2025 Q2 2025 Q3 2025 Q4 2025 FY 2025 Q1 2026 Q2 2026 YTD 2026 Product Revenue $76.3 $81.3 $93.3 $96.8 $347.8 $88.0 $99.2 $187.2 Royalties Revenue 74.0 68.6 65.1 71.7 279.4 69.6 84.2 153.9 Contract and Other Revenue 16.4 22.3 20.1 21.8 80.
Slide 19: Product Overview
Product Overview Industry-leading Chips and Silicon IP
Slide 20: Chips
Chips Server Module Chipsets Providing memory bandwidth, • DDR5 RDIMM capacity, and power efficiency to • DDR5 MRDIMM unleash the performance of • LPDDR5X SOCAMM2 CPUs and accelerators Client Module Chipsets • DDR5 CU/CSODIMM • LPDDR5 LPCAMM2 Chips Silicon IP Innovations 20
Slide 21: DDR5 RDIMM Chipset
DDR5 RDIMM Chipset Industry-leading Performance and Margin • Compliant with latest JEDEC spec up to 9600 MT/s • Wide margin IO design with advanced programmability • Exceeds JEDEC reliability requirements Optimized Power • Frequency-based power optimization Best-in-class Debug and Serviceability • I
Slide 22: DDR5 MRDIMM 12800 Chipset
DDR5 MRDIMM 12800 Chipset Leading Performance • Supports industry-standard MRDIMM 12800 • Full chipset solution • Advanced clocking, control and power management • Supports standard and tall (high capacity) form factors • Common architecture with RDIMM 8000+ to allow flexibility and scalability in s
Slide 23: LPDDR5X SOCAMM2 Server Module Chipset
LPDDR5X SOCAMM2 Server Module Chipset • First in a planned family of LPDDR-based server module chipsets for future AI systems • Full chipset for JEDEC-standard LPDDR5X SOCAMM2 • Supports data rates up to 9.6 Gb/s • Provides module configuration, telemetry, and localized, efficient power conversion L
Slide 24: LPCAMM2 Memory Module Chipset
LPCAMM2 Memory Module Chipset • Supports wide range of PC performance and capacity use cases • Supports data rates to 10666 MT/s • I2C and I3C Basic bus serial interface • Excellent power conversion efficiency • Programmability features for customization LPCAMM2 Module with PMIC5200 and SPD Hub 24
Slide 25: DDR5 CSODIMM/CUDIMM Chipsets
DDR5 CSODIMM/CUDIMM Chipsets • Support wide range of PC performance and capacity use cases • Support data rates to 9600 MT/s • I2C and I3C Basic bus serial interface • Excellent power conversion efficiency • Programmability features for customization DDR5 CSODIMM with Client Clock Driver, PMIC5120 a
Slide 26: Silicon IP
Interface IP • HBM Silicon IP • • GDDR LPDDR Enabling accelerated computing • PCI Express with high-performance interfaces and hardware-level security • CXL Security IP • Root of Trust • MACsec • IPsec • UET-TSS Chips • IME Silicon IP Innovations
Slide 27: Interface IP: Memory Interface and Interconnect IP
Interface IP: Memory Interface and Interconnect IP Video Memory Controllers Interconnect Controllers Compression DDR LPDDR GDDR HBM CXL PCI Express MIPI VESA FEC Application CSI-2/ DSC/ DP/ 4 4X/5X/5T 6/7 2/2E 3/3E 4/4E 2.0 3.1 6.3 7.0 DSI-2 VDC-M HDMI Focus Data Center AI/Edge Automotive Government
Slide 28: Security IP: Protecting Data at Rest, in Motion, and in Use
Security IP: Protecting Data at Rest, in Motion, and in Use Cipher Root of Trust Network Security Crypto Cores Provisioning Engines Application Firmware IPsec Key Programmable MACsec UET-TSS IME Crypto TRNG Infrastructure Focus Controlled TLS Management Data Center N/A AI/Edge Automotive N/A N/A Gov
Slide 29: Rambus Labs
Next-Gen Memory Rambus Labs Enabling next-generation data centers through innovation, Post-Quantum research and development Computing Security Chips Silicon IP Innovations
Slide 30: Key Areas of Focus for Rambus Labs
Key Areas of Focus for Rambus Labs Security for AI/ML Next-Gen Memory Secure and Reliable Strategic Customer & and Post-Quantum Architectures and Memory Systems Product Roadmap Computing Performance Support 30
Slide 31: Thank you
je — Thank you~.