Micron Technology, Inc. · NASDAQ:MU
Micron Technology — Flash Memory Summit 2007
32 slides from Micron Technology's conference presentation, August 2007
Slide 1: The Inconvenient Truths of NAND Flash Memory
The Inconvenient Truths of NAND Flash Memory Jim Cooke (jcooke@micron.com) Applications Engineering Director Micron Technology, Inc. Santa Clara, CA USA August 2007 1
Slide 2: Agenda
Agenda • NAND Flash Differences – MLC vs. SLC – Architecture, Features, and Performance Comparisons • NAND Error Modes – Program Disturb – Read Disturb – Data Retention – Endurance – Wear Leveling – ECC Fixes Almost Everything Santa Clara, CA USA August 2007 2
Slide 3: All NAND Flash Devices Are Not Created Equal
All NAND Flash Devices Are Not Created Equal Differences include: • Cell types • Architectural • Performance • Timing parameters • Command set Open NAND Flash Interface (ONFI) helps to address many of these Santa Clara, CA USA August 2007 3
Slide 4: Cell Types – MLC vs. SLC
Cell Types – MLC vs. SLC Features MLC SLC Bits per cell 2 1 Voltage 3.3V 3.3V, 1.8V Data width (bits) x8 x8, x16 Architecture Number of planes 2 1 or 2 Page size 2,112–4,314 bytes 2,112 bytes Pages per block 128 64 Reliability NOP (partial page programming) 1 4 ECC (per 512 bytes) 4+ 1 Endurance (ER
Slide 5: 2Gb, 2K-Page SLC NAND Architecture
2Gb, 2K-Page SLC NAND Architecture Santa Clara, CA USA August 2007 5
Slide 6: 2Gb, 2K-Page, 72nm, SLC Performance
2Gb, 2K-Page, 72nm, SLC Performance Micron (72nm SLC) 2Gb die 2K Page Performance 35.00 31.62 30.00 25.00 23.85 20.00 M B /s e c 15.00 10.00 7.02 5.81 5.00 0.00 0.00 0.00 0.00 Page Read Cache Read 2Plane Page Read Page Program Program Pge 2Plane Program 2Plane Program Cache Page Page Cache Mode NAND
Slide 7: Two-Plane Features
Two-Plane Features Device is divided into two physical planes, odd/even blocks Users have the ability to: • Concurrently access two pages for read • Erase two blocks concurrently • Program two pages concurrently The page addresses of blocks from both planes must be the same during two-plane RE
Slide 8: 4Gb, Two-Plane, 2K-Page SLC NAND Architecture
4Gb, Two-Plane, 2K-Page SLC NAND Architecture Santa Clara, CA USA August 2007 8
Slide 9: 4Gb, 2K-Page SLC NAND Performance
4Gb, 2K-Page SLC NAND Performance Micron (72nm SLC) 4Gb die 2K Page Performance 40.00 37.62 35.00 33.50 30.00 28.94 25.00 M B /s e c 20.00 19.05 15.00 12.94 9.56 10.00 7.74 5.00 0.00 Page Read Cache Read 2Plane Page Page Program Program Pge 2Plane Program 2Plane Program Read Cache Page Page Cache Mo
Slide 10: 8Gb, Two-Plane, 2K-Page MLC NAND Architecture
8Gb, Two-Plane, 2K-Page MLC NAND Architecture Santa Clara, CA USA August 2007 10
Slide 11: 8Gb, 2K-Page MLC Performance
8Gb, 2K-Page MLC Performance Micron (72nm MLC) 8Gb die 2K Page Performance 45.00 40.00 35.00 30.00 27.06 MB/sec 25.00 20.51 19.92 20.00 15.00 10.00 5.58 6.49 5.00 3.00 3.25 0.00 Page Read Cache Read 2Plane Page Program 2Plane 2Plane Page Read Program Pge Cache Program Program Page Page Cache Mode NA
Slide 12: 16Gb, Two-Plane, 4K-Page MLC NAND Architecture
16Gb, Two-Plane, 4K-Page MLC NAND Architecture Santa Clara, CA USA August 2007 12
Slide 13: Two-Plane, 4K-Page MLC NAND Architecture
Two-Plane, 4K-Page MLC NAND Architecture Micron (55nm MLC) 16Gb die 4K Page Performance 40.00 37.42 35.00 32.41 30.00 27.30 25.00 M B /s e c 20.00 15.00 9.56 10.00 7.73 4.28 4.79 5.00 0.00 Page Read Cache Read 2Plane Page Page Program Program Pge 2Plane 2Plane Read Cache Program Page Program Page Ca
Slide 14: Open NAND Flash Interface
Open NAND Flash Interface Future Micron NAND Flash devices support the ONFI specification Micron is a founding member of ONFI The ONFI 1.0 specification is available at http://www.onfi.org/ ONFI founders: Santa Clara, CA USA August 2007 14
Slide 15: NAND Error Modes
NAND Error Modes Program Disturb Read Disturb Data Retention Endurance Santa Clara, CA USA August 2007 15
Slide 16: Let’s Get Orientated: NAND Architecture
Let’s Get Orientated: NAND Architecture Block Architecture I/O I/O I/O I/O NAND architecture is Control String based on independent Gate blocks Memory Cell Blocks are the smallest erasable units 64 pages Float per block* Gate Pages are the smallest programmable units • Partial pages can be Pag
Slide 17: Program Disturb
Program Disturb Cells not being programmed receive I/O I/O I/O I/O elevated voltage stress Programmed Stressed cells Cells Unselected 10V • Are always in the block being Page: programmed Selected 20V • Can either be on pages not Page: selected, or in a selected page Stressed Unselected Cells but
Slide 18: Reducing Program Disturb
Reducing Program Disturb Program pages in a block sequentially, from page 0 to page 63 (SLC) or 127 (MLC) Minimize partial-page programming operations (SLC) It is mandatory to restrict page programming to a single operation (MLC) Use ECC to recover from program disturb errors Santa Clara, CA
Slide 19: Read Disturb
Read Disturb Cells not being read receive I/O I/O I/O I/O elevated voltage stress Stressed cells are Unselected • Always in the block being Page: 5V Selected read 0V • Always on pages not Page: Stressed being read Unselected Cells Charge collects on the Page: 5V floating gate causing the cell
Slide 20: Reducing Read Disturb
Reducing Read Disturb Rule of thumb for excessive reads per block between ERASE operations • SLC – 1,000,000 READ cycles • MLC – 100,000 READ cycles If possible, read equally from pages within the block If exceeding the rule-of-thumb cycle count, then move the block to another location and era
Slide 21: Data Retention
Data Retention I/O I/O I/O I/O Charge loss/gain occurs on the floating gate over time; device threshold voltage Charge Loss trends to a quiescent level Cell is undamaged; block can be reliably erased and reprogrammed Note: Circuit structures and voltages are representative only. Details vary by
Slide 22: Improving Data Retention
Improving Data Retention Limit PROGRAM/ ERASE cycles in blocks that require long retention Limit READs to reduce read disturb Infrequently cycled blocks have longer 5 yr retention Frequently cycled blocks Retention 2 yr have shorter retention required (arbitrary time) 0.5 yr Block Cycles 10 cyc
Slide 23: Endurance
Endurance I/O I/O I/O I/O PROGRAM/ERASE cycles cause charge to be trapped in the dielectric Damaged Cells Causes a permanent shift in cell characteristics— not recovered by erase Observed as failed program or erase status Blocks that fail should be retired (marked as bad and no longer used)
Slide 24: Endurance Recommendations
Endurance Recommendations Always check pass/fail status (SR0) for PROGRAM and ERASE operations • Note: READ operations do not set SR0 to fail status If fail status after PROGRAM, move all block data to an available block and mark the failed block bad Use ECC to recover from errors Write data
Slide 25: Wear Leveling
Wear Leveling Wear leveling is a plus on SLC devices where blocks can support up to 100,000 PROGRAM/ ERASE cycles Wear leveling is imperative on MLC devices where blocks typically support less than 10,000 cycles If a block was erased and reprogrammed every minute, the 10,000 cycling limit woul
Slide 26: Wear Leveling (continued)
Wear Leveling (continued) An 8Gb MLC device contains 4,096 independent blocks Using the previous example, if the cycles were distributed over 4,096 blocks, each block would be programmed less than 3 times (vs. 10,800 cycles if the same block is cycled) If perfect wear leveling was performed on
Slide 27: ECC Can Fix Everything (well, almost)
ECC Can Fix Everything (well, almost) Understand the target data-error rate for your particular system Understand the use model that you intend for your system Design the ECC circuit to improve the raw-bit error rate (BER) of the NAND Flash, under your use conditions, to meet the system’s targ
Slide 28: ECC Code Selection Is Becoming Even More Important
ECC Code Selection Is Becoming Even More Important 1.0E-25 t=5 4 t=6 3 1 2 t= t= 1.0E-23 t= t= 1.0E-21 Application Bit Error Rate 1.0E-19 1.0E-17 For For SLC SLC 1.0E-15 A A code code with with aa correction correction =0 threshold threshold of of 1 1 is is sufficient t 1.0E-13 sufficient 1.0E-11 1.
Slide 29: Another Option: Embedded MMC (eMMC)
Another Option: Embedded MMC (eMMC) The complexities of future MLC require increased attention; the ECC algorithm, for example, is becoming more and more complex, moving from 4+ bits to 8+ bits in the future A managed interface addresses the complexities of current and future NAND Flash devices;
Slide 30: Micron Solutions: Managed NAND (eMMC)
Micron Solutions: Managed NAND (eMMC) MLC NAND + MMC 4.2 version controller device Highspeed solution: Hostselectable x1, x4, and x8 I/Os 52 MHz clock speed (MAX) – 416 Mb/s data rate (MAX) Fully backward compatible with previous MMC systems ECC, wear leveling, and block management 12
Slide 31: Conclusions
Conclusions NAND Flash is the lowest cost, nonvolatile memory available today Complexities of MLC NAND require increased logic and software design All of these complexities are addressed through the use of the controller included with eMMC Santa Clara, CA USA August 2007 31
Slide 32: Thank You
Thank You ©2007 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any