Lattice Semiconductor Corporation · NASDAQ:LSCC
Lattice Semiconductor — Investor Presentation (June 2010)
39 slides from Lattice Semiconductor's investor presentation, June 2010
Slide 1: Lattice Wireless Solutions
LATTICE WIRELESS SOLUTIONS June 2010
Slide 2: Mid-Range FPGA Positioning
MID-RANGE FPGA POSITIONING High Fast SerDes Ultra-High High Speed I/O Ultra-High FPGA DSP/MACs FPGA Big Memory High Gross High Performance Margins Performance / Density SerDes High Speed I/O DSP/MACs Mid-Range Lower Price FPGA Lower Power Big Memory Mid-Range Performance Low No SerDes Density Low Lo
Slide 3: Lattice Two-Part FPGA Strategy
LATTICE TWO-PART FPGA STRATEGY Lead in Mid-Range FPGAs Vertical Market Low Power, Low Cost Focused Solutions Lattice Wireless Solutions June 2010 Page: 3 Lattice Semiconductor Confidential
Slide 4: Market Recognizes ECP3 Leadership
MARKET RECOGNIZES ECP3 LEADERSHIP Lattice Wireless Solutions June 2010 Page: 4 Lattice Semiconductor Confidential
Slide 5: Lattice ECP3 Key Features
LATTICE ECP3 KEY FEATURES • Low cost/low power, high value – 17K to 149K LUT4s – 36K to 303K bits distributed RAM – Up to 586 I/O • Embedded 3.2Gbps SERDES – Up to 16 channels – Supports CPRI/OBSAI, SRIO – Supports PCI Express, Ethernet (GbE/ SGMII & XAUI), SMPTE • Full featured sysDSP blocks – Up t
Slide 6: Lattice ECP3: Static Power Competitive
LATTICE ECP3: STATIC POWER COMPETITIVE Blank Device Power* (W) Virtex-6 LXT Virtex-5 LXT Stratix IV GX Stratix II GX Arria II GX Spartan-6 LXT Cyclone IV GX ECP3 K LUT4s • Power Optimizations • Variable channel lengths • Optimized transistors • Improved routing defaults & algorithms * Power Calculat
Slide 7: Lattice ECP3: Total Power Advantage
LATTICE ECP3: Total Power Advantage Total Power* (W) Stratix II GX 392% higher Virtex-5 LXT Virtex-6 LXT 207% higher 256% higher Arria II GX 174% higher Stratix IV GX 163% higher Spartan-6 LXT Cyclone IV GX 104% higher 52% higher ECP3 ECP3 offers Significantly Lower Total Power K LUT4s Optimized to
Slide 8: Lattice ECP3 Family Overview
LATTICE ECP3 FAMILY OVERVIEW Device ECP3-17 ECP3-35 ECP3-70 ECP3-95 ECP3-150 LUTs (K) 17 33 67 92 149 EBR SRAM Blocks 38 72 240 240 372 EBR SRAM (Kbits) 700 1,327 4,420 4,420 6,850 Distributed RAM (Kbits) 36 68 145 188 303 18x18 Multipliers 24 64 128 128 320 3.2Gbps SERDES Channels 4 4 12 12 16 Maxi
Slide 9: 2nd Generation Cost/Power/Performance Optimized SERDES
2ND GENERATION COST/POWER/PERFORMANCE OPTIMIZED SERDES • Low cost SERDES – Support for chip to chip & backplane apps – Industry leader with proven signal integrity in low cost wire-bond packages • Data rates from 150Mbps to 3.2Gbps – Support for key 3G standards like XAUI, HiGig, SRIO, 3G SMPTE • Ji
Slide 10: Lattice ECP3 SERDES Overview
LATTICE ECP3 SERDES OVERVIEW • LatticeECP3 features up to 16 embedded 3.2Gbps SERDES • Each SERDES Channel contains independent: – 8b/10b encoding/decoding & Byte Boundary Detect logic – Polarity adjust – Clock tolerance compensation logic and elastic buffer logic • Each group of four SERDES and its
Slide 11: Lattice ECP3 SERDES Block Diagram
LATTICE ECP3 SERDES BLOCK DIAGRAM ANALOG PCS SERDES Recovered Clock Elastic Buffer Receiver Read Clock 3.125 Gbps Byte CTC Down ! 8/10 bits Deserializer! Polarity! EQ! Boundary FIFO! Sample! OR 1:8/1:10! Adjust! Detect,! FIFO! 16/20 bits 8b/10b Decoder! Receive Data Bypass Bypass Bypass Bypass Seria
Slide 12: Lattice ECP3 PCS: Supported Packet Protocols
LATTICE ECP3 PCS: SUPPORTED PACKET PROTOCOLS Supported Gigabit PCI Serial XAUI PHYs Ethernet* Express RapidIO Soft IP SGMII (Optional) PCIe PHY State XAUI PCS GbE State Soft Logic Machine Soft Logic Mach/Auto- Soft Logic Negotiation Framing XAUI State Clock RX State Machine LTSSM Tolerance Machine E
Slide 13: sysI/O Interface
sysI/O INTERFACE • Broad range of I/O standards Bank Bank – LVCMOS, LVTTL, LVPECL, LVDS – HSTL, SSTL class I & II Bank Bank – PCI LVDS Up to 1Gbps • Programmable slew rates Bank Bank • Six general purpose I/O banks per device – Multiple compatible I/O standards in a bank SERDES • External memory int
Slide 14: sysMEM Block RAM
sysMEM BLOCK RAM Single Port Dual Port Pseudo-Dual Port • 18Kbit blocks 16,384 X 1 16,384 X 1 16,384 X 1 • 390MHz performance 8,192 X 2 8,192 X 2 8,192 X 2 4,096 X 4 4,096 X 4 4,096 X 4 • Fully synchronous 2,048 X 9 2,048 X 9 2,048 X 9 – Single port, dual port 1,024 X 18 1024 X 18 1,024 X 18 – Pseud
Slide 15: High Performance Embedded Dual Slice DSP Block
HIGH PERFORMANCE EMBEDDED DUAL SLICE DSP BLOCK • Enhanced 3rd generation sysDSP architecture – Fully cascadable – New modes (MMAC and adder tree) – Backwards compatible with ECP2M sysDSP block – Dual-slice architecture • Higher performance, finer control • Independent ALU operation • Programmable mu
Slide 16: Agenda
AGENDA • Next Gen Base Station Topologies • Status of Current Lattice Wireless IP Solutions • Design S/W and IP Lattice Wireless Solutions June 2010 Page: 16 Lattice Semiconductor Confidential
Slide 17: Wireless Market Dynamics
WIRELESS MARKET DYNAMICS • 4G moves from development to deployment – WiMAX and LTE (OFDMA Based) – iPhone phenomena: Increased backhaul capacity, IP based Looking Into The Future • Wireline/wireless convergence – Femtocells • Focus on low cost service delivery, CAPEX/ OPEX – Cost reductions of exist
Slide 18: Base Station Evolution
BASE STATION EVOLUTION Yesterday: Monolithic Deployment Electrical (Macro Base Station) cable WAN • Most current deployments have the base stations backhaul Transport & co-located near the antenna Baseband PA Processing • The RF transceiver and Power Amplifier (PA) are located within the Base Statio
Slide 19: RRU & Wireless Baseband Opportunities for ECP3
RRU & WIRELESS BASEBAND OPPORTUNITIES FOR ECP3 • Fast follower SRIO – Focus on cost Lattice IP reduction path/ performance upgrade 3rd party IP • Low power solution CPRI/OBSAI JESD204a – Important for OPEX SRIO SRIO – Green Base stations DSP DSP – Remote Radio Units • Initial play with Turbo ECP2M S
Slide 20: Agenda
AGENDA • Next Gen Base Station Topologies • Status of Current Lattice Wireless IP Solutions • Design S/W and IP Lattice Wireless Solutions June 2010 Page: 20 Lattice Semiconductor Confidential
Slide 21: Data Converter Solutions (JESD204A)
DATA CONVERTER SOLUTIONS (JESD204A) • Emerging high speed serial ADC/DAC interface – Alternative to parallel DACs/ADCs offering: • Cost savings (development and BOM) • Enhanced robustness (drive length/error detection) • Reduced on-board interferences (EMI/RFI) • Simplified design/implementation • I
Slide 22: Lattice – NXP JESD204a Partnership
LATTICE – NXP JESD204a PARTNERSHIP • NXP is the first supplier to offer a JESD204A compliant solution for high-speed ADCs and DACs • First device available now from NXP is the ADC1413 – Two-lane device @ 3.125Gbps • Lattice developed JESD204a ‘reference design’ for interop with both ECP2M and ECP3 •
Slide 23: RRU Full Signal Path (Affarii / Lattice)
RRU FULL SIGNAL PATH (AFFARII / LATTICE) • Affarii RRU IP supports up to 20MHz bandwidth: RRU PROCESSOR – 4 channel W-CDMA SERDES CPRI/OSBAI DIGITAL DOWN CONVERSION RX – 2 channel LTE INTERFACE ADC ETHERNET ETHERNET MAC PHY DIGITAL PRE DISTORTION TX • ECP3-150-8 device (# of mults) DAC GENERAL PURPO
Slide 24: RRU Design Solutions (CFR/DPD) from Affarii
RRU DESIGN SOLUTIONS (CFR/DPD) FROM AFFARII Next-Gen Wireless Modulation schemes (LTE/W-CDMA) require special processing functions to maintain the signal integrity of PAs: • Crest Factor Reduction (CFR): – Restricts maximum waveform amplitude – Reduces the signal PAPR while maintaining required sign
Slide 25: RRU Demo & Availability
RRU DEMO & AVAILABILITY • Demonstration of technology can be arranged by appointment with Affarii – Evaluation platform and development tools available Q2 2010 • Fully supported RRU solution with PC based design analysis tools, design support and production API Lattice Wireless Solutions June 2010 P
Slide 26: CPRI (Common Public Radio Interface)
CPRI (COMMON PUBLIC RADIO INTERFACE) Functional Overview Of Lattice IP • Supports the Physical Link layer and portions of S the Data Link layer User C&M y Plane Plane n c • Supports the four standard bit rates of the CPRI Application layer v4.0 specification (user logic) – 614.4 Mbps, 1228.8 Mbps &
Slide 27: CPRI: Addressing Latency Variation
CPRI (COMMON PUBLIC RADIO INTERFACE) Addressing Latency Variation • Main contributors to link delay variation are the Word Alignment block and bridging FIFO • The PCS Rx path in the ECP3 has been updated to allow the Word Alignment delay variation to be measured and made available via and offset reg
Slide 28: CPRI Delay Variation Summary
CPRI DELAY VARIATION Summary Low latency IP Configuration Basic IP Configuration (bridge FIFOs bypassed) Comments Analog SERDES +/- 280 ps +/- 280 ps No change Word Align offset value is WA +/- 1.83 ns Variation measured/offset readable through SCI registers Moved to soft IP, Rx FIFO + Tx FIFO +/- 1
Slide 29: CPRI/OBSAI
CPRI/OBSAI • CPRI – Supports v4.0 (aside from 5G data rate) with built-in low latency variation capabilities • Removes variation induced by clock-domain crossing and Word Alignment uncertainty • Low latency driven by MIMO, network synchronization, and GPS – Low latency demo available, emulates REC-R
Slide 30: Lattice ECP3 SRIO v2.1 - Overview
LATTICE ECP3 SRIO v2.1 - OVERVIEW • Complete SRIO solution – v2.1 IP core, logical layer reference design, RapidFET testing (leverage for RIOLabs) and TI interop • Integrated hardware : SERDES + low cost FPGA on one chip • Intellectual Property: Lattice supplied SRIO v2.1 core – Supports 1x/2x/4x co
Slide 31: SRIO v2.1 Protocol Support (1x/2x/4x)
SRIO v2.1 PROTOCOL SUPPORT (1x/2x/4x) Streaming support • Maintenance • I/O Logical Layer optional • Doorbells (interrupts) Common Transport Transport Layer Link State Machine Channel Alignment (2x/4x) Physical Layer Clock Tolerance Compensation 8b/10b User Logic/ Ref Design Word Alignment Soft IP P
Slide 32: SRIO Update
SRIO UPDATE • SRIO beta IP core – Currently available as 1x/2x @ 3.125Gbps and 4x @ 2.5Gbps – 2x/4x configurations tested as loopback only – Final release of IPexpress core with logical layer interfaces in late July • Current demo is 1x @ 3.125G Gbps on ECP3 – Utilizes the ECP3 AMC and interoperates
Slide 33: Agenda
AGENDA • Next Gen Base Station Topologies • Status of Current Lattice Wireless IP Solutions • Design S/W and IP Lattice Wireless Solutions June 2010 Page: 33 Lattice Semiconductor Confidential
Slide 34: ispLEVER Design Software
ispLEVER DESIGN SOFTWARE • LatticeECP3 devices supported in ispLEVER software version 7.1 or later • Comprehensive tool set – Unleashes designers’ productivity • Logic synthesis – Mentor Graphics Precision RTL – Synplicity Synplify • Timing simulation – Mentor Graphics ModelSim • Linux, Unix & PC Ve
Slide 35: Key Lattice ECP3 IP Cores Released
KEY LATTICE ECP3 IP CORES RELEASED Communications DSP Connectivity •10Gb+ Ethernet MAC •CIC •DDR1 / DDR2 / DDR3 •TS-MAC •CORDIC •PCI Express Endpoint x1, x4 •SGMII & GbE •DA-FIR •PCS PIPE •CPRI •Block Convolutional Encoder •PCI_MT - 32-bit / PCI_MT - 64-bit •XAUI PCS •Block Viterbi Decoder •PCI_T -
Slide 36: Other Next-Gen IP Technologies to Consider
OTHER NEXT-GEN IP TECHNOLOGIES TO CONSIDER • CESOP: Circuit Emulation Services Over Packet (ITU-T G.8261/Y.1361) – Also known as Synchronous Ethernet – Required for synchronization of TDM data transported over Packet Network – Looking at 3rd Party as possible source – Underlying technology for PWE3
Slide 37: Wireless Summary
WIRELESS SUMMARY • Key areas of focus: RRU, BTS/BBU and backhaul – RF/RRU • RRU signal path solutions (CFR/DPD) • JESD204a serial data converter i/f (NXP, others planned as available) • Standard parallel ADC/DACs supported as well – BB data transport • Low latency CPRI • OBSAI (available as ref desi
Slide 38: Lattice ECP3 Value Proposition
LATTICE ECP3 VALUE PROPOSITION • Broad range of SERDES channels with enhanced signal integrity – Supports commonly used wireless protocols: CPRI, JESD204a, SRIO, GbE/SGMII and PCIe • High logic & memory capacity at lower price – Up to 150K LUTs & 7Mbits embedded RAM • High performance sysI/O – DDR3,
Slide 39: Lattice Wireless Solutions
LATTICE WIRELESS SOLUTIONS June 2010 http://www.latticesemi.com/solutions/marketsolutions/wireless
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