Teledyne Technologies Incorporated · NYSE:TDY
Teledyne Technologies — Technical Presentation
41 slides from Teledyne Technologies's technical presentation
Slide 1: ESIstream 62B64B: Get started with VCK190 loopback package
ESIstream 1 The Efficient Serial Interface ESISTREAM 62B64B Get started with VCK190 loopback package VERSAL AI CORE XCV1902-2MSEVSVA2197
Slide 2: Summary
Summary Acquire RX data (62-bit) 1 Hardware setup 5 Using Vivado Integrated Logic Analyzer (ILA) From Vivado project creation Design example top file 2 to link synchronization 6 testbench simulation Application Note: 3 Project overview 7 Create an ESIstream Gigabit Transceivers Block Design (.bd) fr
Slide 3: Hardware Setup
Hardware Setup ESIstream The Efficient Serial Interface
Slide 4: Hardware setup: Ordering information
Hardware setup Ordering information ❑ VCK190 Versal AI Core Evaluation kit product web page. ❑ Avnet: EK-VCK190-G by AMD Xilinx Evaluation & Development Kits | Avnet ❑ SAMTEC VITA 57.4 FMC+ HSPC Loopack Card product web page ❑ Avnet REF-197618-01 by Samtec Hardware Development Tools | Avnet ❑ Mouser
Slide 5: Hardware setup
5 Hardware setup Connect cables and loopback board on J51 Connect XM107 loopback board Connect power cable Connect USB C JTAG + UART cable between PC and VCK190
Slide 6: Hardware setup
6 Hardware setup Power-ON VCK190 Evaluation Kit ON Switch ON SW13 OFF
Slide 7: User interface
7 User interface Push-Buttons (x2), Led (x4), Switches (x4) LED3: BE or CB STATUS LED1: TX and RX IP READY LED2: RX LANES READY LED0: UART READY and VALID STATUS ‘1’ PB0 SYNC PB1 RST GT ‘0’ TX DATA CTRL 1 ‘1’ (ramp enabled) TX CLOCK BIT ENABLE ‘1’ (enabled) TX and RX PRBS ENABLE ‘1’ (enabled) TX DIS
Slide 8: Project overview
Project overview ESIstream The Efficient Serial Interface
Slide 9: Project overview: FPGA loopback
9 Project overview LoopBACK FPGA BOARD data TX 11 Serial Lanes GENERATOR (RAMP) DATA RX CHECK
Slide 10: From Vivado project creation to link synchronization
From Vivado project creation to link synchronization
Slide 11: Create Vivado project
11 Create Vivado project ❑ Open Vivado 2021.1 ❑ Click on Tools > Run Tcl Script… ❑ Launch script_64b.tcl available in loopback/ package directory. ❑ Once project creation has completed… ❑ Click on Recent projects view to open it.
Slide 12: Generate Device image
Generate Device image #% Iopback 4b - [C © \90/leopback/script 64b/loc file fait Flow Tools Reports Window Layout View Help Quick Access &, wee Flow N EI rrovect MANAGER- loopback oto Aca Sources sources Properties Language Templates alzlei+ : F PCataleg Design Sources ( Y PINTEGRATOR Create Block D
Slide 13: Load Device image
13 Load Device image Open hardware Manager
Slide 14: Load Device image
14 Load Device image Click on Open target and Auto Connect
Slide 15: Load Device image
15 Load Device image Click on Program device and Program
Slide 16: Start link synchronization
16 Start link synchronization Maximize ILA window
Slide 17: Start link synchronization
17 Start link synchronization ❑ Check UART is ready and ESIstream TX and RX transceivers are ready: LED0 ON and LED 1 ON ❑ Push SYNC button (PB0) ❑ The loopback communication between ESIstream TX and RX through the loopback board has started. ❑ Check RX LANES are ready, LED2 ON. ❑ Check there is no
Slide 18: Acquire RX data (62-bit)
Acquire RX data (62-bit) Using Vivado Integrated Logic Analyzer (ILA)
Slide 19: Acquire data in Vivado using JTAG and ILA
19 Acquire data in Vivado using JTAG and ILA. In hardware manager, click on play button.
Slide 20: ILA Analog view
20 ILA Analog view Select all lanes + right-click, then click on Waveform > Analog Settings…
Slide 21: ILA Analog view
21 ILA Analog view Select Hold and click on OK.
Slide 22: Design example top file testbench simulation
Design example top file testbench simulation
Slide 23: Launch Vivado Simulator
23 Launch Vivado Simulator Click on Run simulation and Run Behavioral Simulation to simulate the whole design. Top testbench
Slide 24: Run the simulation for 70 µs
24 Run the simulation for 70 µs Click on Play button.
Slide 25: Run the simulation for 70 µs (zoom)
25 Run the simulation for 70 µs (zoom)
Slide 26: Application Note: Create an ESIstream Gigabit Transceivers Block Design
Application Note: Create an ESIstream Gigabit Transceivers Block Design (.bd) from scratch on Versal.
Slide 27: Application Note
27 Application Note Create ESIstream Gigabit transceivers block design (.bd) from scratch.
Slide 28: Application Note
28 Application Note Create ESIstream Gigabit transceivers block design (.bd) from scratch. Search for gt_bridge_ip Double click on Transceivers Bridge IP
Slide 29: Application Note
29 Application Note Create ESIstream Gigabit transceivers block design (.bd) from scratch. Double click on Transceivers Bridge IP
Slide 30: Application Note
30 Application Note Create ESIstream Gigabit transceivers block design (.bd) from scratch.
Slide 31: Application Note
31 Application Note Create ESIstream Gigabit transceivers block design (.bd) from scratch.
Slide 32: Application Note
32 Application Note Create ESIstream Gigabit transceivers block design (.bd) from scratch.
Slide 33: Application Note
33 Application Note Create ESIstream Gigabit transceivers block design (.bd) from scratch.
Slide 34: Application Note
34 Application Note Create ESIstream Gigabit transceivers block design (.bd) from scratch.
Slide 35: Application Note
35 Application Note Create ESIstream Gigabit transceivers block design (.bd) from scratch.
Slide 36: Application Note
36 Application Note Create ESIstream Gigabit transceivers block design (.bd) from scratch.
Slide 37: Application Note
37 Application Note Create ESIstream Gigabit transceivers block design (.bd) from scratch. ❑ Make external hsclk0_lcplllock, hsclk1_lcplllock signals from gt_quad_base, gt_quad_base_1 and gt_quad_base_2 ❑ Tools > Run Tcl Script… ❑ Launch make_external_lcplllock.tcl ❑ The Validate design and Create H
Slide 38: Application Note
38 Application Note Create ESIstream Gigabit transceivers block design (.bd) from scratch.
Slide 39: UART
ESIstream The Efficient Serial Interface
Slide 40: UART - FPGA interface protocol: Write command
40 UART - FPGA interface protocol Write command ▪ The design embeds a UART slave which uses the ▪ Register Write operation: following configuration: The UART master must send the data in the order described on the figure below ▪ Baud rate: 115200 to be able to write a FPGA register. ▪ Data Bits: 8 F
Slide 41: UART - FPGA interface protocol: Read command
41 UART - FPGA interface protocol Read command ▪ The design embeds a UART slave which uses the ▪ Register Read Operation following configuration: The UART master must send the data in the order described on the figure below ▪ Baud rate: 115200 to be able to read a FPGA register value. Firstly, the m