Asml Holding Nv · EURONEXT:ASML
Asml Holding Nv — Bank of America Merrill Lynch Technology Conference 2011
32 slides from Asml Holding Nv's conference presentation, Jun 1, 2011
Slide 1: Bank of America Merrill Lynch Technology Conference
Bank of America Merrill Lynch Technology Conference New York Craig DeYoung – Vice President Investor Relations June 1, 2011 Exhibit 99.1
Slide 2: Safe Harbor
Safe Harbor "Safe Harbor" Statement under the US Private Securities Litigation Reform Act of 1995: the matters discussed in this document may include forward-looking statements, including statements made about our outlook, realization of backlog, IC unit demand, financial results, average selling pr
Slide 3: ASML's strategy
ASML’s strategy To be a technology leader in lithographic systems and software for semiconductor manufacturing, thus enabling our customers to increase the functionality of microchips while reducing the cost and power consumption per function on a chip
Slide 4: ASML Headquarters in Veldhoven, the Netherlands
ASML Headquarters in Veldhoven, the Netherlands ASML: the number 2 semiconductor equipment supplier in the world in 2010
Slide 5: Agenda
Agenda Business Overview Market ASML EUV update Outlook and summary
Slide 6: Business Overview
Business Overview
Slide 7: Total net sales M€ by quarter, 2006-2011
629 949 919 183 742 1,452 942 930 844 277 1,069 958 934 697 555 1,176 1,053 955 494 581 1,521 1,000 2,000 3,000 4,000 5,000 6,000 2006 2007 2008 2009 2010 2011 Q4 Q3 Q2 Q1 Total net sales M€ 3,582 3,768 Numbers have been rounded for readers’ convenience. 2,954 1,596 4,508
Slide 8: Q1 results - highlights
Q1 results - highlights Net sales of € 1,452 million, 63 systems shipped valued at € 1,284 million, service and field option sales at € 168 million Gross margin of 44.7% Operating margin of 31.0% Net system bookings of 40 systems, € 845 million Backlog at € 3,330 million, 134 systems with ASP of € 2
Slide 9: Key financial trends 2010 – 2011
Key financial trends 2010 – 2011 Consolidated statements of operations M€ Numbers have been rounded for readers’ convenience. Q1 10 Q2 10 Q3 10 Q4 10 Q1 11 Net Sales 1,069 1,176 1,521 1,452 Gross profit Gross margin % 40.3% 43.0% 43.6% 45.0% 44.7% R&D costs SG&A costs Income from operations Operatin
Slide 10: Backlog breakdown by technology, region and end-use
ArF immersion 74% Korea 25% DRAM 27% Foundry 22% New systems Used systems Total systems Units Value M€ 3,262 3,330 ASP M€ 28.4 3.6 24.9 Backlog in value per March 27, 2011 Total value M€ 3,330 Technology KrF 19% I-Line 2% Region (ship to location) USA 18% Taiwan 17% Europe 10% Japan 8% End-use IDM 1
Slide 11: Market
Market
Slide 12: Business environment
Business environment • Semiconductor manufacturers have shown caution in assessing economic impact of Japanese earthquake on their supply chain and end-product markets • Although direct impact to the electronics industry world- wide seems limited, it has caused some of our customers to review their
Slide 13: 3mma IC revenue, inventory and inventory days
3mma IC revenue, inventory and inventory days - 3mma IC inventory value (left) 3mma IC revenues (left) 3mma IC consumption: revenues ± inventory value change (left) 3mma Inventory days (right) Consumption decreased in March, whereas revenues increased, causing growing IC inventory level Source: VLSI
Slide 14: DRAM
DRAM Source: DRAMeXchange (5/5/2011), ASML MCC Further recovery of contract prices leads tier manufacturers at low 5x nm (closer) to profitability <Customer litho system utilizations high> (6x), 1Gb (5x H), 1 Gb (5x L), 1 Gb (4x H), 2 Gb Estimated DRAM cash costs in Q1/11 (avg. production node in nm
Slide 15: NAND
NAND MAIN NAND SPOT & CONTRACT PRICES (01/2008 - 2011YTD) 16Gb NAND SLC SPOT PRICE 16Gb NAND SLC CONTRACT PRICE 32Gb NAND MLC SPOT PRICE 32Gb NAND MLC CONTRACT PRICE 64Gb NAND TLC SPOT PRICE 64Gb NAND TLC CONTRACT PRICE 300 mm cash-costs for 3x nm 32 Gb 2 b/c MLC NAND between 3,2 and 4,0 USD SLC spo
Slide 16: ASML EUV update
ASML EUV update
Slide 17: Technology - EUV
Technology - EUV NXE:3100 second generation EUV Three NXE:3100 shipped to date, 3 more to go Progress ongoing to reach target throughput by year end Customer process development started Infrastructure development transitioning to optimization phase (masks, resist, metrology, etc) Revenue recognition
Slide 18: Why EUV? EUV supports IC & Lithography roadmap towards <10nm
LOGIC DRAM NAND / Slide 18 Why EUV? EUV supports IC & Lithography roadmap towards <10nm Year of production start XT:1400 XT:1700i AT:1200 XT:1900i NXT:1950i NXE:3100 NXE:3300 Notes: 1. R&D solution required 1.5~ 2 yrs ahead of Production 2. EUV resolution requires 7nm diffusion length resist 3. DPT
Slide 19: Consumers are the winners
Consumers are the winners Shrink drives manufacturing cost down Note: data iSupply, March 2009. High quality Flash 1000 10000 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 $2,305 for 1Gigabyte (GB) $0.17 for 1 GB
Slide 20: Shrink drives device complexity which drives litho opportunity
Shrink drives device complexity which drives litho opportunity due to a growing number of critical litho layers Source: ASML Marketing (03/11), 300mm wafers only Node 9x,6x 9x, 6x 6x ,4x 6x, 4x 4x, 3x Node 6x, 4x 6x, 4x 4x, 3x 3x, 2x 2x, 1x Average MPU immersion layers 2008 2009 2010 2011 2012 2008
Slide 21: Increasing immersion layers per node, per year with shrink in memory too
Increasing immersion layers per node, per year with shrink in memory too Node 8x, 6x 6x, 5x 5x, 4x 4x, 3x 3x, 2x Node 5x, 4x 4x, 3x 4x, 3x 3x, 2x 2x, 1x Source: ASML Marketing (03/11), 300mm wafers only Average DRAM immersion layers 2008 2009 2010 2011 2012 2008 2009 2010 2011 2012 Average NAND imme
Slide 22: Typical Patterning Schemes for Critical Layers
Logic NAND DRAM Logic NAND DRAM 32nm 2x nm 3x nm 22nm 1x nm 2xnm ArFi Spacer DPT Spacer DPT Litho DPT 2x Spacer Spacer DPT EUV Typical Patterning Schemes for Critical Layers 2011 2013 DPT = Double Patterning Organic BARC Resist Hard Mask Expose Develop Inorganic BARC Metrology Hard Mask Etch Strip &
Slide 23: Cost Impact of Double Patterning
Cost Impact of Double Patterning - 0.5 1.0 1.5 2.0 2.5 3.0 Logic NAND DRAM Logic NAND DRAM ALL 32nm 2x nm 3x nm 22nm 1x nm 2xnm - ArFi 1D Spacer 1D Spacer 2x Litho- Etch Double Spacer 2D Spacer EUV Reticle Strip/Clean Etch Metrology CVD Litho chemicals Track Litho Source: ASML Strategic Marketing
Slide 24: Cycle Time Impact of Double Patterning
Cycle Time Impact of Double Patterning - 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Logic NAND DRAM Logic NAND DRAM ALL 32nm 2x nm 3x nm 22nm 1x nm 2xnm - ArFi 1D Spacer 1D Spacer 2x Litho- Etch Double Spacer 2D Spacer EUV Strip/Clean Etch Metrology CVD Litho Source: ASML Strategic Marketing
Slide 25: Reduced cost/complexity drives EUV adoption
Spacer Li Reduced cost/complexity drives EUV adoption and secures it’s role in lithography for the next decade EUV lowers overall costs for customer, while increasing litho costs € 70.82 * € 46.44 * * Source: ASML Strategic Marketing; Cost of Technology model incl. Capex & Opex – NAND Example Cost p
Slide 26: ASML's Unique Holistic Litho Optimisation & Control
Source-Mask Optimization Optical Proximity Correction Litho Manufacturability Check LithoCell Monitoring & Control Application-Specific Scanner Tuning Integrated Metrology Process Feedback ASML’s Unique Holistic Litho Optimisation & Control of future low k1, DP and EUV litho processes • Optimize sca
Slide 27: Scanner Optimisation & Control via Wafer Metrology & Computational Litho
Stages Illuminator Lens Sensors ASML Scanner Optimisation & Control enabled through Wafer Metrology & Computational Litho Computational Lithography Optimization and Tuning for CD Wafer Metrology Setup and Control of CD and Overlay Programmable Wavefront Programmable pupil and polarization CD and Ove
Slide 28: Section Summary
Section Summary Low k1 Double Patterning Lithography enables extension of immersion Lithography bridging the gap until single patterning EUV is available However, Double Patterning presents significant Cost, Process Control, and Cycle Time manufacturing challenges Advanced Optical Metrology enables
Slide 29: Outlook and summary
Outlook and summary
Slide 30: Q2 2011 outlook
Q2 2011 outlook Order intake between € 900 million – €1 billion Net sales around € 1.5 billion Gross margin about 45% R&D at € 150 million SG&A at € 55 million ASML expects 2011 total revenue clearly above € 5 billion
Slide 31: Cash return
€ 0 € 50 € 100 € 150 € 200 € 250 Cash return € 2.7B cash & cash equivalents at end Q1 2011 € 1 B / 24 month share buy back program in progress 21% of program executed until wk 19 7 million shares repurchased at an average price of € 29.66 Weekly updates available on ASML’s website Dividend for 2010
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