Technoprobe Spa · MIL:TPRO
Technoprobe Spa — Investor Day (April 2025)
71 slides from Technoprobe Spa's investor day presentation, Apr 14, 2025
Slide 1: Capital Market Day, 14th April 2025
14th April 2025 : (ry) | Capital Market Day ~) TECHNOPROBE
Slide 2: Disclaimer
Disclaimer This document has been prepared by Technoprobe S.p.A. (the preparing the corporate accounting documents, declares in “Company”) solely for use in the presentation of the Technoprobe accordance with paragraph 2, Article 154-bis of Legislative Decree Group (the “Group”) and its financial re
Slide 3: Agenda
Agenda 01 | Our Vision & Strategy Stefano Felici - CEO 02 | Market Perspective Marco Prea - CCO 03 | Technology & Testing Joe Parks - CTO 04 | Financial Outlook Stefano Beretta - CFO
Slide 4: 01 | Our Vision & Strategy
Agenda 01 | Our Vision & Strategy Stefano Felici - CEO
Slide 5: So far so good: leading MEMS probe card player
01 | Our Vision & Strategy So far so good Leading player in designing & manufacturing of MEMS Probe Cards for logic chips 60% 2024 Market Share
Slide 6: So far so good: customer awards
01 | Our Vision & Strategy So far so good Intel’s 2025 EPIC NEW Supplier Award Customer satisfaction and reputation as cornerstone values TSMC’s Excellent Performance Award 2024
Slide 7: So far so good: strong focus on innovation
01 | Our Vision & Strategy So far so good Strong focus on innovation +600 Patents
Slide 8: Extensive global presence and local footprint
01 | Our Vision & Strategy So far so good Extensive global presence and widespread local footprint
Slide 9: Technoprobe evolution
01 | Our Vision & Strategy Technoprobe evolution CAGR % 2019-2024 1.019 922 937 815 SAM* ($Mn) +11% 811 Technoprobe 557 574 562 +20% Revenues ($Mn) 463 442 377 229 Partnership Advantest 2019 2020 2021 2022 2023 2024 2025 Acquisition Acquisition Acquisition Partnership Microfabrica Harbor Electronics
Slide 10: Our positioning in the testing space
01 | Our Vision & Strategy Our positioning in the testing space FRONT END BACK END Wafer fabrication Wafer Testing Final Testing & pre-assembly Assembly Packaging Level Level preparation Wafer Level Socket Singulated Die System Level Testing Advanced Packaging Device Interface Board Probe Card
Slide 11: Our positioning in the semiconductor probe card market
01 | Our Vision & Strategy Our positioning in the semiconductor Probe Card market Semiconductor Probe Card by application MEMORY NON MEMORY DRAM & HBM Other memory HPC RF SENSOR/POWER Other ASIC GPU/CPU
Slide 12: The Probe Card
01 | Our Vision & Strategy The Probe Card
Slide 13: The Probe Card
01 | Our Vision & Strategy The Probe Card Mechanics PCB Interconnection Ceramic plates Probe Head Contact probes
Slide 14: The Probe Card
01 | Our Vision & Strategy The Probe Card Mechanics PCB Interconnection Ceramic plates Probe Head Contact probes
Slide 15: Our business model
01 | Our Vision & Strategy Our business model Design Manufacturing Assembly Wafer Testing Level Mechanics Manufacturing partners PCB & other suppliers Interconnection Probe head Ceramic plates Contact probes Final Testing Level Device Interface Manufacturing partners Boards & other suppliers
Slide 16: Built an open eco-system of partnerships
01 | Our Vision & Strategy Built an open eco-system partnerships Accelerate growth of complete Priority suppliers Probe Card and Final Test of PCB Interfaces by acquisition of DIS Joint Development Projects Joint Development Projects to deliver superior customer to share knowledge value in SOC and M
Slide 17: Challenges & strategic setting
01 | Our Vision & Strategy Challenges & strategic setting Evolution of chip technology → Continuous investments in R&D 1 (more than Moore) Scaling slow down as enabler for chiplets, → M&A as accelerator of 3D architectures and new materials technological development → Strategic partnerships Increase
Slide 18: What's next?
01 | Our Vision & Strategy What’s next? FRONT END BACK END Wafer Testing Level Final Testing Level Probe Card Device Interface Board
Slide 19: What's next?
01 | Our Vision & Strategy What’s next? Consolidate the leading positioning in all test segments FRONT END Drive advancements in Logic Semiconductor Testing Proliferate high-speed, high-voltage, radio frequency and silicon photonics Enter the High Bandwidth Memory (HBM) segment BACK END Strengthen p
Slide 20: Agenda
Agenda 01 | Our Vision & Strategy Stefano Felici - CEO 02 | Market perspective Marco Prea - CCO 03 | Technology & Testing Joe Parks - CTO 04 | Mid-term Plan Stefano Beretta - CFO
Slide 21: 02 | Market Perspective
Agenda 02 | Market Perspective Marco Prea - CCO
Slide 22: The Probe Card market ($Mn)
02 | Market Perspective The Probe Card market ($Mn) Forecast History 3.000 2.500 2.000 Datacenter & AI 1.500 1.000 Auto & Industrial PC & Consumer mobile 500 Electronics - 2019 2020 2021 2022 2023 2024P 2025E 2026E 2027E 2028E CAGR % 2019-2024: +6.5% CAGR % 2024-2028: +6.2% Source: Yole – Semiconduc
Slide 23: The Probe Card market by segment
02 | Market Perspective The Probe Card market By segment ($Mn) CAGR % 2019-2024 CAGR % 2024-2028 1.783 2.443 +6.5% 3.133 +6.2% 100% 90% 80% 70% 1.151 1.638 +7.3% 2.060 +5.9% 60% 50% 40% 30% 20% +4.9% 632 805 1.053 10% 0% Logic Memory 2019 2024 2028 Source: Yole – Semiconductor Test Consumables marke
Slide 24: Logic Probe Card by technology
02 | Market Perspective Logic Probe Card by technology ($Mn) CAGR % 2019-2024 CAGR % 2024-2028 1.151 1.638 +7.3% 2.060 +5.9% 100% 125 220 194 +9.3% 90% 80% 70% +10.9% +6.6% 557 60% 937 1.212 50% 40% 30% 262 286 +1.8% 357 20% Others 10% 207 MEMS 222 +1.4% 270 Vertical 0% 2019 2024 Cantilever 2028 Sou
Slide 25: Our reference markets
02 | Market Perspective Our reference markets 2024 Logic Probe Card market 2024 MEMS Logic Probe Card $1,6 Bn $937 Mn Cantilever MEMS Vertical Other Market Share: 34% Market Share: 60% Source: Yole – Semiconductor Test Consumables market monitor Q3 2024 (Sept.2024) – rounded figures.
Slide 26: Final Testing market – Advanced PCBs
02 | Market Perspective Final Testing market – Advanced PCBs Advanced PCBs ($Mn) CAGR % 2019-2024 CAGR % 2024-2028 778 1.034 +5.9% 1.214 +3.9% 100% 90% 210 290 +6.7% 351 80% 70% 60% 50% 40% 568 744 +5.6% 863 +3.9% 30% 20% 10% Burn-in Boards Device Interface Boards 0% 2019 2024 2028 Source: Yole Test
Slide 27: Our reference markets
02 | Market Perspective Our reference markets 2024 Advanced PCB for semiconductor 2024 Final Test DIB market $1 Bn $744 Mn * Device Interface Boards Burn-in Boards Market Share: 6% Market Share*: 8% Source:Yole Test Interface Board market monitor Q3 2024 (Sept.2024) – rounded figures. (*) Based on D
Slide 28: Focus on Memory market
02 | Market Perspective Focus on Memory market Semiconductor market ($Bn) Next Generation Memory market ($Bn) 1.000 30 900 800 25 700 20 600 500 15 400 300 10 200 5 100 - 0 2024P 2025E 2028E 2024 2025 CAGR % 2019-2024: +13% Source: Yole and Precedence Research Estimates.
Slide 29: Key messages | Market perspective
02 | Market Perspective Key messages 02 | Market perspective MEMS Logic PC Final Test HBM Ever-growing market for Immediate exposure New challenge leading edge technology to an expanded SAM & opportunity Key positioning on Technological MEMS technology as a technological advances breakthroughs from
Slide 30: Agenda
Agenda 01 | Our Vision & Strategy Stefano Felici - CEO 02 | Market Perspective Marco Prea - CCO 03 | Technology & Testing Joe Parks - CTO 04 | Financial Outlook Stefano Beretta - CFO
Slide 31: 03 | Technology & Testing
Agenda 03 | Technology & Testing Joe Parks - CTO
Slide 32: Growth drivers & trajectories
03 | Technology & Testing Growth drivers & trajectories FRONT END BACK END Wafer Testing Level Final Testing Level Probe Card Device Interface Board
Slide 33: Growth drivers & trajectories
03 | Technology & Testing Growth drivers & trajectories FRONT END Drive advancements in Logic Semiconductor Testing Proliferate high-speed, high-voltage, radio frequency and silicon photonics Enter the High Bandwidth Memory (HBM) segment BACK END Strengthen positioning in Final Testing
Slide 34: Growth drivers & trajectories
03 | Technology & Testing Growth drivers & trajectories FRONT END Drive advancements in Logic Semiconductor Testing
Slide 35: Semiconductor technology trend
03 | Technology & Testing Semiconductor technology trend Industry motivation behind advanced packaging How to continue drive for increase compute power in light of transistor density rate lower and die size growth limitations? Transistor scaling rate is decreasing Die size scaling limited by reticle
Slide 36: Solution: die disaggregation and advanced packaging
03 | Technology & Testing Semiconductor technology trend Solution: die disaggregation and advanced packaging • Improved wafer-level yield with smaller chiplet • Optimizing performance with mixed functionality capabilities • Memory • Co-packaged optics • Allows for mixed technology node application a
Slide 37: Role of test in disaggregated world
03 | Technology & Testing Role of test in disaggregated world FRONT END BACK END Wafer fabrication Wafer Testing Final Testing & pre-assembly Assembly Packaging Level Level preparation Easy example: single die into a package
Slide 38: Role of test in disaggregated world
03 | Technology & Testing Role of test in disaggregated world FRONT END BACK END Wafer fabrication Wafer Testing Final Testing & pre-assembly Assembly Packaging Level Level preparation Any missed screening at sort directly impacts final yield Not good die Yield ~ HIGH Cost of Front End coverage is b
Slide 39: Role of test in disaggregated world
03 | Technology & Testing Role of test in disaggregated world FRONT END BACK END Wafer fabrication Wafer Testing Final Testing & pre-assembly Assembly Packaging Level Level preparation What about four die?
Slide 40: Role of test in disaggregated world
03 | Technology & Testing Role of test in disaggregated world FRONT END BACK END Wafer fabrication Wafer Testing Final Testing & pre-assembly Assembly Packaging Level Level preparation Paramount to screen at Front End Test Large Yield Impact Front End Test coverage For each mis-screened die: Not goo
Slide 41: Advanced packaging vs standard
03 | Technology & Testing Advanced packaging vs standard Standard Manufacturing cost 1x Yield loss (YL)1 FRONT END
Slide 42: Advanced packaging vs standard
03 | Technology & Testing Advanced packaging vs standard Standard Advanced Manufacturing cost Manufacturing cost 1x Nx Yield loss Cost of yield (YL)1 (YL)N Product cost is a SUM Cost of yield is NOT a sum but a PRODUCT FRONT END
Slide 43: Role of test in disaggregated world
03 | Technology & Testing Role of test in disaggregated world Front End Test coverage is more critical True Known Good Die required! SOLUTION more test at probe = more Probe Cards FRONT END
Slide 44: Technoprobe as advanced packaging enabler
03 | Technology & Testing Technoprobe as advanced packaging enabler High-speed Fine pitch and ultra-large pin count Short, ultra short and RF-specific needles Necessary to effectively probe HPC technology to manage high speed interconnect and HBM’s and all leading-edge product IO, including SiPh Hig
Slide 45: Growth drivers & trajectories
03 | Technology & Testing Growth drivers & trajectories FRONT END BACK END Wafer Testing Level Final Testing Level Probe Card Device Interface Board
Slide 46: Growth drivers & trajectories
03 | Technology & Testing Growth drivers & trajectories FRONT END Drive advancements in Logic Semiconductor Testing Proliferate high-speed, high-voltage, radio frequency and silicon photonics Enter the High Bandwidth Memory (HBM) segment BACK END Strengthen positioning in Final Testing
Slide 47: Growth drivers & trajectories
03 | Technology & Testing Growth drivers & trajectories FRONT END Proliferate high-speed, high-voltage, radio frequency and silicon photonics
Slide 48: A hungry world of wideband applications
03 | Technology & Testing A hungry world of wideband applications Future demands on the network will be driven by a combination of factors: Exponential increase in number Bandwidth-hungry applications & type of connected things Future demands Increasing reliance on the cloud FRONT END
Slide 49: A hungry world of wideband applications
03 | Technology & Testing A hungry world of wideband applications Future demands on the network will be driven by a combination of factors: Analog radio frequency Satellite communications and Exponential increase in number sensing, automotive radar, & type of connected things mobile communication,…
Slide 50: A hungry world of wideband applications
03 | Technology & Testing A hungry world of wideband applications Future demands on the network will be driven by a combination of factors: Silicon photonics Chiplet to chiplet interconnect / photonics-driven computing Bandwidth-hungry applications Future demands FRONT END
Slide 51: A hungry world of wideband applications
03 | Technology & Testing A hungry world of wideband applications Future demands on the network will be driven by a combination of factors: Silicon photonics Technoprobe technologies integrated in the same product enable… Bandwidth-hungry applications Fine pitch probing → alignment with advanced pac
Slide 52: A hungry world of wideband applications
03 | Technology & Testing A hungry world of wideband applications Future demands on the network will be driven by a combination of factors: Chiplet probing High density and high-speed IO inside chiplet demand for high-performance probe needles Future demands Increasing reliance on the cloud FRONT EN
Slide 53: Growth drivers & trajectories
03 | Technology & Testing Growth drivers & trajectories FRONT END BACK END Wafer Testing Level Final Testing Level Probe Card Device Interface Board
Slide 54: Growth drivers & trajectories
03 | Technology & Testing Growth drivers & trajectories FRONT END Drive advancements in Logic Semiconductor Testing Proliferate high-speed, high-voltage, radio frequency and silicon photonics Enter the High Bandwidth Memory (HBM) segment BACK END Strengthen positioning in Final Testing
Slide 55: Growth drivers & trajectories
03 | Technology & Testing Growth drivers & trajectories FRONT END Enter the High Bandwidth Memory (HBM) segment
Slide 56: HBM shipments (Exabytes)
03 | Technology & Testing DRAM & HBM: complexity as driver to new products 45 40 35 HBM shipments (Exabytes) 30 25 • HBM demand continues to grow 20 15 • HBM bandwidth requirements 10 almost double gen-gen 5 0 2024P 2025E 2026E 2027E 2028E HBM2 HBM2E HBM3 HBM4 HBM4E HBM5 (and beyond) Source: Yole DR
Slide 57: DRAM & HBM testing
03 | Technology & Testing DRAM & HBM testing DRAM and HBM are typically tested with microcantilever probing technologies. For both applications Technoprobe is leveraging on Vertical MEMS solution and on a unique PC Most advanced HBM and Next Generation architecture. products are becoming more challe
Slide 58: Growth drivers & trajectories
03 | Technology & Testing Growth drivers & trajectories FRONT END BACK END Wafer Testing Level Final Testing Level Probe Card Device Interface Board
Slide 59: Growth drivers & trajectories
03 | Technology & Testing Growth drivers & trajectories FRONT END Drive advancements in Logic Semiconductor Testing Proliferate high-speed, high-voltage, radio frequency and silicon photonics Enter the High Bandwidth Memory (HBM) segment BACK END Strengthen positioning in Final Testing
Slide 60: Growth drivers & trajectories
03 | Technology & Testing Growth drivers & trajectories BACK END Strengthen positioning in Final Testing
Slide 61: FusionLink
03 | Technology & Testing FusionLink We have applied the disaggregation to test interface hardware Main motherboard Best technology: printed circuit board (PCB) Device substrate Best technology: high density interconnect (HDI) Probe substrate Best technology: multi-layer organic (MLO) BACK END
Slide 62: Growth drivers & trajectories
03 | Technology & Testing Growth drivers & trajectories FRONT END Advanced Packaging Radio frequency & silicon photonics HBM Strengthen Expand Enter new markets BACK END leadership leadership FusionLink
Slide 63: Agenda
Agenda 01 | Our Vision & Strategy Stefano Felici - CEO 02 | Market Perspective Marco Prea - CCO 03 | Technology & Testing Joe Parks - CTO 04 | Financial Outlook Stefano Beretta - CFO
Slide 64: 04 | Financial Outlook
Agenda 04 | Financial Outlook Stefano Beretta - CFO
Slide 65: Mid-terms scenario
04 | Financial Outlook Mid-terms scenario → Testing solution for Advanced Packaging 1 Technological complexity evolution → Increase in demand for high-precision tests → AI will lead the growth for many market segments 2 Market trends → Expansion of memory semiconductor segments → Technological sover
Slide 66: Market trends & revenues path
04 | Financial Outlook Market trends & revenues path (€Mn) Estimated Organic Growth: 543 Market Assumptions Mid-single digit 2% 2% 2025 Growth Destocking and inventory containment 14% + Low single digit 11-13% measures expected to remain sluggish Expansion in volume for data center to 35% + High dou
Slide 67: Market trends & revenues path
04 | Financial Outlook Market trends & revenues path (€Mn) Estimated Organic Growth: 850-900 543 Market Assumptions Mid-single digit 2% 2% Industry recovery 14% 11-13% 35% 36-38% Growth driven by data centers 49% 46-48% Positive impact of Edge AI 2024 2025 Target Model
Slide 68: Profitability profile
04 | Financial Outlook Profitability profile EBITDA margin Operating Leverage 38%- 40% Product mix 25% Integration costs Innovation / ramp-up costs Smooth EBITDA trajectory up to 38-40% 2024 Target model
Slide 69: Capex
04 | Financial Outlook Capex (€Mn) FY 2024 FY 2022 FY 2023 FY 2024 Target Model Others 13% Revenues 549 409 543 DIS Tech Technoprobe Italy 11% 37% Capex 84 73 100 Capex as % of Revenues 15% 18% 18% 8% - 10% Yee Wei 39%
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Slide 71: Capital Market Day
aan & Capital Market Day