Synopsys, Inc. · NASDAQ:SNPS
Synopsys — Technical Presentation (2019)
23 slides from Synopsys's technical presentation, 2019
Slide 1: Full Chip CDM Simulation With Package Layout Included for Connectivity and Charge Distribution
2019 International ESD Workshop Full Chip CDM Simulation With Package Layout Included for Connectivity and Charge Distribution Jordan Davis, Samsung Electronics, Yuri Feinberg, Silicon Frontline, Sung-Jun Song, Chanhee Jeon, Han-gu Kim, Samsung Electronics
Slide 2: Biography
Biography Career Started EE Career at ON Semiconductor in March 2008 as design intern ON Semiconductor ESD discrete device & process designer, 2009 - 2017 Samsung Electronics, HQ, Foundry Division, ESD verification focusing on deployment of full chip CDM for FA and signoff 2017 - present Edu
Slide 3: Abstract
Abstract There are several advanced EDA tools that can simulate full chip CDM stress. However, they only take into account the IC layout through the use of GDS, CCI, or SVDB databases[1] in order to determine the charge distribution for a related CDM stress level. CDM stress is strongly influenced b
Slide 4: Overview
Overview The Whys: Why is package data needed for full chip CDM? What package data is needed? What makes thin film packaging different? The Hows: Overcoming the caveats of full chip CDM for thin film applications The process The Cases: Case 1: Physical failure not found without packag
Slide 5: Overview
Overview Full chip CDM simulations can be influenced by the package Package attributes that increase influence: Long wires in thin film package increase discharge path resistances Thin film packaging has a dominant effect on CDM charge distribution since packaging is major charge source Packa
Slide 6: Package Data Needs In CDM Simulations
Package Data Needs In CDM Simulations The need for package data in full chip CDM simulations Package level connectivity can strongly influence the CDM current path When no package data available only simple assumptions can be made about connectivity False High Real Error Resistance False Error
Slide 7: Package Data Needs In CDM Simulations
Package Data Needs In CDM Simulations The need for package data in thin film cases Package trace resistance can be an issue Ideal connectivity between IC pins and chip pads can provide good results in classical packages where trace resistances are small in comparison to global ESD path resistan
Slide 8: Package Data Needs – Thin Film
Package Data Needs – Thin Film The problem with chip simulations alone FLR packaging orients the IC ‘substrate up’ during CDM testing This orientation applies the charge to the top metal layer When packaging is taken into account, charge distribution is significantly modified due to change in
Slide 9: Package Data Needs – Thin Film
Package Data Needs – Thin Film Package models improve connectivity and ESD path considerations, but don’t aide in charge distribution accuracy Resistive package model adds trace resistance to discharge paths Package netlist model does not supply geometric information. Accurate charge distribu
Slide 10: Simulation Methodology – Thin Film
Simulation Methodology – Thin Film The Solution: Incorporate layout geometry in simulation DB Resistance model is not needed. Package traces are seen as another layer of interconnect Esra simulation tool automatically calculates resistances for interconnect. Charge distribution is handled a
Slide 11: Simulation Methodology – Thin Film
Simulation Methodology – Thin Film Charge distribution is calculated using Silicon Frontline’s proprietary model Charge distribution for FLR package is based on: Package and IC layer shapes Proximity of shapes to the charged plate Accuracy verified through comparison with FA results and silic
Slide 12: Overcoming the caveats of full chip CDM
Overcoming the caveats of full chip CDM The Solution: It’s not trivial… Package layout has to be converted to compatible format AutoCAD dwg to dxf to gdsii Scaling and orientation manipulation Typically layout files have 1D scaling coefficient to account for expansion of thin film durin
Slide 13: Overcoming the caveats of full chip CDM
Overcoming the caveats of full chip CDM The Result: Fully integrated IC and package layouts Chip on film (COF) with film level routing (FLR) package 2019 International ESD Workshop Page 13
Slide 14: Case 1 – Failure Not Found without Package
Case 1 – Failure Not Found without Package In testing it was found that a display driver IC had CDM failures in a given cell Initial simulation findings did not match physical failures Most failures in simulation found near center of die Fail Locations Physical / Simulation 2019 International ES
Slide 15: Case 1 – Failure Not Found without Package
Case 1 – Failure Not Found without Package To improve simulation accuracy netlist package model was generated and included It was assumed increased discharge path resistance due to package traces was the issue Simulated failure locations were still at center of die not matching failure analysis 2
Slide 16: Case 1 – Failure Not Found without Package
Case 1 – Failure Not Found without Package It was proposed that metal traces in the package were impacting CDM charge distribution Layout geometry from package was incorporated into the database used for CDM simulations Resulting simulations found physical failure locations matching cell where p
Slide 17: Case 1 – Failure Not Found without Package
Case 1 – Failure Not Found without Package Specific cell where failure occurred No violations in cell when packaging not used in simulation Buffer Cell Numerous violations found when Photon Emission Analysis simulated with package data 2019 International ESD Workshop Page 17
Slide 18: Case 1 – Failure Not Found without Package
Case 1 – Failure Not Found without Package Charge distribution was impacted by presence of package layout metal Top metal layer shown for IC Results from package included simulation showing concentrated charge storage density on specific nodes induced by FLR layout. Changes to the FLR layout cor
Slide 19: Case 2 – Failures Found Without Package
Case 2 – Failures Found Without Package Simulation of device was done with no package data All pads from same die-net were shorted Results accurately identified failure location Other false errors were also present and some at higher stress value than actual failure point Circuit Representation
Slide 20: Case 2 – Failures Found Without Package
Case 2 – Failures Found Without Package Failure locations observed in silicon were also found by Esra simulation Inclusion of package data did not significantly reduce false violations nor change real violation detection Photon Emission Analysis Simulation Results 2019 International ESD Workshop P
Slide 21: Conclusions
Conclusions Full chip CDM simulations can be a great tool for sign-off and failure analysis assistance. In considering the accuracy of CDM simulations there are cases where the package of a device can impact the results In cases where the package metal is much larger than top metal of the IC impa
Slide 22: Conclusions
Conclusions While not all thin film packaging cases require this level of accuracy, it is important to be aware of all the possible caveats in performing full chip CDM simulations Package netlist use insufficiencies Impacts of package metal frame layout Non-trivial conversion and inclusion in
Slide 23: Acknowledgements and References
Acknowledgements and References A special thanks to all of the team at Silicon Front Line for the extensive work done to bring these additional capabilities to fruition. 1. Dolphin Abessolo-Bidzo et al., “A Study of HBM and CDM Layout Simulations Tools”, EOS/ESD 2018 2. Melanie Etherton et al., “Stu