Asml Holding Nv · EURONEXT:ASML
Asml Holding Nv — Investor Day (November 2024)
50 slides from Asml Holding Nv's investor day presentation, Nov 18, 2024
Slide 1: ASML Investor Day: Global market trends, technology roadmap, ESG
Public Christophe Fouquet Global market trends Industry & ASML's technology roadmap ESG ASML Investor Day Veldhoven, The Netherlands November 14, 2024 President and Chief Executive Officer Small Talk 2024 Exhibit 99.2
Slide 2: Key messages: AI opportunity and ASML's EUV and holistic lithography
Public • The Semiconductor Industry remains strong and Artificial Intelligence is expected to create further opportunity as major investments in supercomputing are happening and the entire industry is preparing to insert AI in all critical future applications • Our industry will require major innova
Slide 3: Customer trust and partnership remains at the core of ASML's strategy
Public A Customer trust and partnership remains at the core of ASML’s strategy Seon-Yong Cha, SK Hynix CTO We expect that our ability to scale EUV technology into the next decade and extend our versatile holistic lithography portfolio could place ASML at the heart of the AI opportunity. This would c
Slide 4: From chips everywhere to AI chips everywhere
Public We see our society going from chips everywhere to AI chips everywhere Gen AI opens endless opportunities, expected to add 6-13T$ value to GDP by 2030 Connected world Climate change and resource scarcity Social and economic shifts Automation Healthcare, medical tech Technological sovereignty W
Slide 5: AI has strong potential to drive entire industry forward
Public Internet of Things Cloud infrastructure Edge computing Energy transition Automation Healthcare, medical tech Technological sovereignty Working, learning remotely Hyperconnectivity Electrification, smart mobility Agricultural innovation Smarter use of limited resources AI has strong potential
Slide 6: Global semi sales >$1T by 2030
Public Cloud infrastructure Edge computing Energy transition Automation Healthcare, medical tech Technological sovereignty Working, learning remotely Hyperconnectivity Electrification, smart mobility Agricultural innovation Smarter use of limited resources We reconfirm our view calling for global se
Slide 7: The semiconductor ecosystem has considerable means to drive innovation
Public Page 7 Semi Equipment Hardware ASML Peers Semi Non-Semi Loss in 2023 The semiconductor ecosystem has considerable means to drive innovation Despite a market downturn, the ecosystem generated over $865B EBIT in 2023 Logic IDM Foundry Wafers Distributor E D A A u to m o ti v e PC S m a rt p h o
Slide 8: Ecosystem has reinvested around half of its EBIT in innovation
Public The semiconductor ecosystem has reinvested around half of its EBIT to drive long-term innovation and growth, and we expect this to continue Page 8 2015 2016 2017 E B IT [ B $ ] 2018 437R & D [ B $ ] 2019 2020 2021 2022 900 800 700 600 500 400 300 200 100 0 2023 449 540 616 564 616 883 817 865
Slide 9: Moore's law for computing power is alive and well
Public Moore’s law for computing power is alive and well Transistors per package continue to double every two years enabling one trillion by 2030 Source: nn Kelleher, ntel, “Moore’s law – now and in the future”, ntel investor day Feb 17, 2022 T ra n s is to rs P e r P a c k a g e ( lo g ) Aspiring t
Slide 10: High performance compute demand beyond Moore's law
Public High Performance Compute Demand Beyond Moore’s Law We expect that Generative AI will demand an acceleration of Moore’s law Energy use could set a ceiling on training capability moving forward if not addressed Page 10 C o m p u te p e r p a c k a g e [ F L O P s ] 2x/2yrs E n e rg y u s e p e
Slide 11: Generative AI computing power outpaces Moore's law
Public High Performance Compute Generative AI, high-performance computing power outpaces Moore’s law In 2030, >70% of data center demand could be driven by AI, representing >90% of Gen AI FLOPs Page 11 C o m p u te p e r p a c k a g e [ F L O P s ] 2x/2yrs E n e rg y u s e p e r p a c k a g e [ J ]
Slide 12: Supercomputer architecture has potential to meet AI needs
Public Generative AI, high-performance computing power outpaces Moore’s law Supercomputer architecture has the potential to meet the needs of AI Page 12 High Performance Compute C o m p u te [ F lo p s ] 2x/2yrs Moore’s law E n e rg y u s e [ J ] (Energy per flop)-0.4x/2yrs Energy per flop + Compute
Slide 13: Architecture cost must be reduced to enable AI opportunity
Public Generative AI, high-performance computing power outpaces Moore’s law Architecture cost must be reduced to fully enable AI opportunity Aurora supercomputer (HPC and AI applications) delivers 2,000,000,000,000,000,000 FLOPs using ~85K CPUs/GPUS, >20PB memory for computing and >230PB memory for
Slide 14: HPC energy consumption must be addressed
Public Generative AI, high-performance computing power outpaces Moore’s law HPC rapidly growing energy consumption must be addressed to prevent a ceiling on training capability 1952 1960 1968 2008 2016 1023 1021 1019 1017 1015 1013 1011 109 107 105 103 101 T ra in in g c o m p u te ( F L O P s ) D e
Slide 15: New cost and energy challenges must be met to unleash AI
Public Scalability of High-performance computing is endless.. … but new cost and energy challenges must be met to unleash AI opportunity AI computing architecture1 AI architecture cost2 The semiconductor industry needs to deliver the highest computing power / transistor density at the lowest cost, i
Slide 16: AI to accelerate the need for advanced logic roadmap
Public We expect AI applications to accelerate the need for advanced logic roadmap 2018 2020 2023 2025 2027 2029 2031 2033 2035 2037 2039 Future 2D and 3D innovations are paving the way for the next 15 years Page 16November 14, 2024
Slide 17: AI to transform DRAM architecture and volume
Public We expect AI applications to transform DRAM architecture and volume Future DRAM should integrate additional logic functionalities to improve performance & energy efficiency Page 17 “P M can improve performance and energy efficiency of memory-bound workloads by adding additional logic function
Slide 18: Strong transistor growth for logic and DRAM
Public 10 100 1000 2015 2020 2025 2030 So, we continue to anticipate strong transistor growth for both logic and DRAM And we expect the semiconductor demand mix to shift towards advanced logic and DRAM Page 18 D R A M G b p ro d u c e d [ 1 0 1 8 / m o n th ] C GR ’15-’23: 18% DRAM Source: Logic his
Slide 19: Cost and energy reduction at the core of process optimization
Public Cost and energy reduction should be at the core of future process optimization 1. Increasing the number of good transistor processed at every step 2. Simplifying the overall process flow 3. Minimizing cost and emission of each processing step 40~80 cycles Page 19 Total cost and total emission
Slide 20: Higher transistor density at lower cost for decades
Public Page 201Source: ASML, excluding innovations in standard cell design G o o d p ri n te d t ra n s is to r / € [ a .u .] 1 ASML has delivered higher transistor density at lower cost for several decades We believe that EUV scalability & holistic lithography can extend our historical trend into t
Slide 21: Higher transistor density at lower cost for decades (overall)
Public Page 211Source: ASML, excluding innovations in standard cell design G o o d p ri n te d t ra n s is to r / € [ a .u .] 1 ASML has delivered higher transistor density at lower cost for several decades We believe that EUV scalability & holistic lithography can extend our historical trend into t
Slide 22: EUV extendibility: ASML's innovations extend EUV benefits
Public 2024 2030 2024 2030 2024 2030 Good printed transistor CO2 Cost of Technology Environmental cost +150% /exposure - 30% /exposure - 50% /exposure EUV Extendibility ASML’s innovations can extend the benefits of EUV lithography More good transistors at lower cost and energy for customers, at incr
Slide 23: ASML's innovations can extend the benefits of EUV lithography
Public Page 23 = Good printed transistors Total lithography cost CO2 ASML’s innovations can extend the benefits of EUV lithography More good transistors at lower cost and energy for customers @ increased profitability for ASML November 14, 2024
Slide 24: ASML intends to innovate on all aspects of lithography value
Public Good printed transistors Resolution ProductivityAccuracyPatterning Yield × × × Operational cost Environmental costSystem cost Lifetime/ + 1 Ton CO2 = 200 EUR + Total lithography cost ASML intends to innovate on all aspects to maximize its product portfolio value nnovation per product (EUV, DU
Slide 25: Customer trust and partnership remains at the core of ASML's strategy
Public ACustomer trust and partnership remains at the core of ASML’s strategy Seon-Yong Cha, SK Hynix CTO We expect that our ability to scale EUV technology into the next decade and extend our versatile holistic lithography portfolio could place ASML at the heart of the AI opportunity. This would co
Slide 26: Semiconductor manufacturers continue to drive shrink
Public We anticipate that semiconductor manufacturers will continue to drive shrink Reducing transistor dimensions likely remains the easiest way to drive density up at reduced cost Page 26 SP: Single Patterning, DP: Double Patterning, QP: Quadruple Patterning, EPE: Edge Placement Error Source: 1Luc
Slide 27: Logic and DRAM drive further critical lithography exposures
Public Logic and DRAM are expected to drive further critical lithography exposures We expect EUV 0.33 NA layers to continue to increase node on node Page 27 2025 2029 - 2030 2025 2029 - 2030 high low high low low high NXE 0.33 NA low high # o f E U V 0 .3 3 N A E x p o s u re s # o f E U V 0 .3 3 N
Slide 28: EUV 0.33 NA enables multi-patterning to single expose conversion
Public EUV 0.33 NA could enable further multi-patterning to single expose conversion Resulting in cost, yield and cycle time benefits for our customers Page 28 2022 2024 2026 2028 2030 2032 Single Expose (EUV 0.33 NA) A v e ra g e p a tt e rn in g c o s t p e r la y e r 2018 2020 LOGIC (LE-LE-LE – l
Slide 29: Conversion results in higher number of EUV exposures 2025-2030
Public EUV 0.33 NA could enable further multi-patterning to single expose conversion Resulting in higher number of EUV exposures for ASML between 2025 and 2030 Page 29 2022 2024 2026 2028 2030 2032 SE (EUV) A v e ra g e p a tt e rn in g c o s t p e r la y e r 64% 25% 17% 58% 33% 3% LE-LE-LE SE (EUV)
Slide 30: 0.55 NA EUV opportunity starts now
Public 0.55 NA EUV opportunity starts now as 0.33 NA EUV transitions to multi-patterning on <26nm pitch critical layers SP: Single Patterning, DP: Double Patterning, QP: Quadruple Patterning Source: 1Luc van den Hove, IMEC , ITF May 21, 2024 0 5 10 15 30 20 Single Expose 0.55 Double Expose 0.55 0.55
Slide 31: High NA EUV enables more design freedom for logic
Public LOGIC: High NA EUV enables more design freedom with 1.5D and 2D designs Single expose simplification reduces process steps, cycle time and improves yield Exposure NXE 1 Exposure NXE 2 Exposure NXE 3 P22 in horizontal direction combined with P28 in vertical direction. Page 31 This multi-exposu
Slide 32: High NA insertion in HVM 2026-27, adoption by end of decade
Public Logic and DRAM are expected to drive further critical lithography exposures Insertion of High NA in high volume manufacturing in 2026-27, adoption by end of the decade 2025 2029 - 2030 DRAMLOGIC 4-6 2-3 Expected average High NA Layers Page 32 2025 2029 - 2030 high low high low low high NXE 0.
Slide 33: High NA EUV optics innovation sets base for EUV roadmap
Public High NA EUV’s latest optics innovation sets the base for our EUV roadmap Picometer stability (1/200 Si atom) achieved on asymmetric mirrors Page 33 NA >0.5 High NA Mirror Metrology at Zeiss Mask level Wafer level NA 0.33 Wafer level Mask level November 14, 2024
Slide 34: EUV source power continues to scale to >1000W
Public EUV source power continues to scale with opportunity to achieve >1000W 740W EUV power demonstrated EUV source power scaling 2010 2015 2020 2025 0 100 200 300 400 500 600 E U V s o u rc e p o w e r [W a tt s ] Products 2030 700 800 900 1000 - measures identified to reach >1000W in the future 1
Slide 35: High NA optics support higher productivity EUV platform
Public High NA EUV optics support the vision of a higher productivity EUV platform EUV performance and productivity can be extended far into the next decade (>2030) 0.33 NA 0.55 NA 0.75 NA Today EXE platform NXE platform System commonality~50% ~95% Future: higher productivity platform Page 35Novembe
Slide 36: 0.75 NA EUV opportunity in the next decade
Public 0.75 NA EUV opportunity is in the next decade when <16nm pitch will be needed Higher productivity platform can be designed to support future Hyper NA needs Page 36 SP: Single Patterning, DP: Double Patterning, QP: Quadruple Patterning Source: 1Luc van den Hove, IMEC , ITF May 21, 2024 Single
Slide 37: Front end 3D integration to complement 2D shrink
Public We expect front end 3D integration to complement 2D shrink in driving density Front end 3D integration challenges will trigger new litho opportunities for all semiconductor products Page 37 Stack LOGIC W-W hybrid W-W Fusion W-W | D-W Fusion Overlay 3D NAND BSPN CFET HVM 2026 >2032 Array CMOS
Slide 38: Holistic lithography should support front end 3D integration
Public Holistic Lithography should support front end 3D integration Metrology and scanner control at pre and post bonding are critical process points needed for overlay Page 38 Pre-bonding CMOS Scanner correction and control ARRAY Scanner and offline metrology 2 1 Actuators Post-bondingBonding ARRAY
Slide 39: Lithography compensates process fingerprints
Public Lithography is a formidable tool to compensate process fingerprints Correction capability increased ~5 orders of magnitude, now @100 000 parameters per exposure Exposure stage 100% of wafers are measured 100% of wafers are processed field-by-field Metrology stage Even Fingers Odd Fingers Grey
Slide 40: Wafer bonding can drive transistor density for DRAM
Public Wafer bonding can drive transistor density increase for DRAM memory 3 scenarios are currently in play for DRAM roadmap, all include bonding and require major innovations Page 40 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 D1c D1d D0a D0b D0c D0d D0e D0f 1) CBA: CMOS Bonded Arr
Slide 41: Wafer bonding can drive transistor density for DRAM
Public Wafer bonding can drive transistor density increase for DRAM memory 3 scenarios are currently in play for DRAM roadmap, all include bonding and require major innovations Page 41 2025 2026 2027 2028 2029 2030 2031 2033 2034 2035 2036 1c 1d 0a 0b 0c D0d D0e D0f 1) CBA: CMOS Bonded Array – CMOS
Slide 42: Wafer bonding can drive transistor density for DRAM
Public Wafer bonding can drive transistor density increase for DRAM memory 3 scenarios are currently in play for DRAM roadmap, all include bonding and require major innovations Page 42 2025 2026 2027 2028 2029 2030 2031 2033 2034 2035 2036 1c 1d 0a 0b 0c D0d D0e D0f 1) CBA: CMOS Bonded Array – CMOS
Slide 43: Wafer bonding can drive transistor density for DRAM
Public Wafer bonding can drive transistor density increase for DRAM memory 3 scenarios are currently in play for DRAM roadmap, all include bonding and require major innovations Page 43 2025 2026 2027 2028 2029 2030 2031 2033 2034 2035 2036 1c 1d 0a 0b 0c 0d 0e 0f 1) CBA: CMOS Bonded Array – CMOS log
Slide 44: Cost of technology remains a major criterion for customers' roadmap
Public Bonding CBA Bonding Cost of technology remains a major criteria for our customers’ roadmap choices EUV scalability and holistic lithography can support future front end 3D integration schemes Page 44 2023 2025 2027 2028 2030 2032 2034 2035 2037 2039 2041 B it c o s t s c a lin g ( $ /G B ) –
Slide 45: Cost of technology remains a major criterion for customers' roadmap
Public Page 45 2023 2025 2027 2028 2030 2032 2034 2035 2037 2039 2041 3D Array performance today; 5 layers 3D Array cost challenge performance of theoretical 125 layers if produced in HVM with today’s capability 3D Array 6F2 / 4F2 6F2 3D Array insertion in 2032 requires 125 layers New DRAM factories
Slide 46: ASML remains committed to greenhouse gas neutrality ambitions
Public ASML remains committed to its greenhouse gas neutrality ambitions Intensifying collaboration in the value chain aimed at accelerating climate action Page 46 Help society limit global temperature rise to 1.5°C Improvement lever 2025 2030 2040 2050 Paris Agreement Category Continue collaboratio
Slide 47: EUV innovations expected to drive energy consumption down
Public 450 400 350 300 250 200 150 100 50 0 Our EUV innovations are also expected to drive EUV energy consumption down Within a 15 year period at customers, we anticipate 80% reduction of energy needed per wafer exposed 2018 2021 2023 2033 Improvement in energy per wafer Total power equivalent 100%
Slide 48: ASML is increasing its engagement with communities
Public Attractive & Inclusive communities STEM ESG innovation Employee giving Contribute to positive improvements and experiences in our communities Increase the talent pool that society needs to solve some of its key challenges Support innovative ideas to solve key ESG challenges Engage with and ca
Slide 49: Forward Looking Statements
Public Forward Looking Statements This document and related discussions contain statements that are forward-looking within the meaning of the U.S. Private Securities Litigation Reform Act of 1995, including statements with respect to our strategy, plans and expected trends, including trends in end m
Slide 50: Thank You
Public THANK YOU