Asm International N.v. · EURONEXT:ASM
Asm International — Analyst and Investor Technology Seminar, Semicon West 2018
45 slides from Asm International's conference presentation, Jul 10, 2018
Slide 1: High Productivity Solutions for Advanced Wafer Processing with New Materials
HIGH PRODUCTIVITY SOLUTIONS FOR ADVANCED WAFER PROCESSING WITH NEW MATERIALS ASM International Analyst and Investor Technology Seminar Semicon West July 10, 2018
Slide 2: Cautionary Note
CAUTIONARY NOTE Cautionary Note Regarding Forward-Looking Statements: All matters discussed in this presentation, except for any historical data, are forward-looking statements. Forward- looking statements involve risks and uncertainties that could cause actual results to differ materially from thos
Slide 3: Outline
OUTLINE › New Materials and 3D: Moore’s law enablers • ASM technology focus: enabling new materials and new device integration roadmaps • Logic scaling • Memory scaling › ALD • ASM ALD Products • Selected applications in Logic, 3D-NAND, DRAM and Emerging Memory › PECVD › Epitaxy › Vertical Furnace ›
Slide 4: Outline
OUTLINE › New Materials and 3D: Moore’s law enablers • ASM technology focus: enabling new materials and new device integration roadmaps • Logic scaling • Memory scaling › ALD • ASM ALD Products • Selected applications in Logic, 3D-NAND, DRAM and Emerging Memory › PECVD › Epitaxy › Vertical Furnace ›
Slide 5: Moore's Law Is Increasingly Enabled by New Materials and 3D Technologies
MOORE’S LAW IS INCREASINGLY ENABLED BY NEW MATERIALS AND 3D TECHNOLOGIES 1990 1995 2000 2005 2010 2015 2020 2025 Scaling enabled by Litho Patterning Multi-Color ESL IEDM 2002 Spacers Self-aligned IEDM 2003 Scaling enabled by Materials IEDM 2007 High-mobility Low-k Materials Strained Si Scaling enabl
Slide 6: Logic Scaling by Materials and 3D
LOGIC SCALING BY MATERIALS AND 3D 2011 FinFET Device • Density scaling (continuing Moore’s law) driving towards higher mobility, lower resistivity and very conformal materials • Future systems will integrate much wider variety of materials • New device architectures will be needed around N3 Next Dev
Slide 7: Memory Scaling by Materials and 3D
MEMORY SCALING BY MATERIALS AND 3D Flash Memory DRAM 2D Planar W CG Capacitor: Cylinder Poly FG Si 2015 SiN W BL Spacer replacement 3D-NAND (SiN /Ox) BWL: CTF (Charge Trap) TiN/W Capacitor: Pillar SiN FFW Low k BL replacement Spacer BWL: 2-Tier TiN/FFW 3D DRAM CTF w/ Tunnel ~2023 Barrier Engineeri
Slide 8: Outline
OUTLINE › New Materials and 3D: Moore’s law enablers • ASM technology focus: enabling new materials and new device integration roadmaps • Logic scaling • Memory scaling › ALD • ASM ALD Products • Selected applications in Logic, DRAM, 3D-NAND and Emerging Memory › PECVD › Epitaxy › Vertical Furnace ›
Slide 9: ASM Products: ALD
ASM PRODUCTS ALD › Pulsar® XP ALD Hf based high-k gate dielectrics ALD metal oxides for etch stops, liners and pattern assist layers Cross-flow reactor Solid source delivery system Pulsar® XP › EmerALD® XP ALD metal gate electrodes ALD metal nitrides for capacitor electrodes Showerhead
Slide 10: FinFET Challenges: ALD Enables Further Scaling in 3D
FINFET CHALLENGES: ALD ENABLES FURTHER SCALING IN 3D 14nm 10nm 22nm Fin Pitch: 60 nm Fin Pitch: 42 nm Fin Pitch: 34 nm Source: Intel Gate Pitch: 90 nm Gate Pitch: 70 nm Gate Pitch: 54 nm Metal Pitch: 80 nm Metal Pitch: 52 nm Metal Pitch: 36 nm • Materials properties and channel length must be unifor
Slide 11: Extendibility of Hafnium Based Gate Oxide and Metal Gate Technology
EXTENDIBILITY OF HAFNIUM BASED GATE OXIDE AND METAL GATE TECHNOLOGY chipworks chipworks 45nm HK first RPMG 22nm HK last RPMG 10nm HK last RPMG Planar FET FinFET FinFET plus additional HK tuning layer 10nm multi-work function metal gate stack TechInsights | 11
Slide 12: ASM Products: PEALD and PECVD
ASM PRODUCTS PEALD AND PECVD › XP8-DCM High productivity single wafer tool for both PEALD and PECVD applications Accommodates up to 8 chambers by DCM PEALD and PECVD can be integrated on the same platform DCM (Dual Chamber Module) | 12
Slide 13: PEALD for Spacer Defined Double/Quadruple Patterning
PEALD FOR SPACER DEFINED DOUBLE/QUADRUPLE PATTERNING Pitch: P ALD SiO2 on resist ALD MOx on resist Hard Mask Etch Pitch: 1/2 P In-situ trimming Spacer Defined Double Patterning (SDDP) with 2nd ALD Spacer ALD in production since 3xnm DRAM, in 3D- NAND and Emerging Memory PEALD SiO2 Spacer Spacer
Slide 14: Current ALD Patterning Spacer Applications
CURRENT ALD PATTERNING SPACER APPLICATIONS Photo Source: TechInsights DRAM (1X) Logic (10~7nm) 3D-NAND Multiple patterning spacers Multiple patterning spacers 1patterning spacer examples examples Bit Line (SDDP) Active STI (SDQP) Fin Formation (SDQP) Emerging Memory Multiple patterning spacers examp
Slide 15: PEALD Processes for Logic Applications
PEALD PROCESSES FOR LOGIC APPLICATIONS TechInsights M0 M0 Capping layers SAC SAC VCT VCG Metal Gate Contact liners SDB Gate spacers Gate fill Fin SiGe Fin IO gate oxides STI liners Leading edge logic devices are using PEALD for many layers, because of the requirement of low thermal budget by using S
Slide 16: PEALD SiN for 3D-NAND Applications
PEALD SiN FOR 3D-NAND APPLICATIONS Samsung VLSI Symp 2009 Raising Contact Landing Pad by PEALD SiN Prevent contact etch punch-through SiN Raising contact landing Pad • PEALD SiN SiN film on Top and Bottom only SiN W SiO SiO Contact Etch. Fewer etch steps and more process latitude to create staircase
Slide 17: Memory Hierarchy and Future Trends
MEMORY HIERARCHY AND FUTURE TRENDS • DRAM and 3D-NAND scaling continues SRAM • Many opportunities for new STT materials and ALD processes in DRAM RAM Performance (speed) new memories FeRAM FeRAM RRAM 3D XPoint NAND New non-volatile memories Non-volatile memories Volatile memories Cost/bit | 17
Slide 18: PEALD Processes for 3D X-Point
PEALD PROCESSES FOR 3D X-POINT • High Quality Low Temperature PEALD SiO2 Gapfill. • Low thermal conductive material Gapfill for next generation. Source:Micron • High Quality Low Temperature PEALD SiO2 liner Source: TechInsights | 18
Slide 19: Outline
OUTLINE › New Materials and 3D: Moore’s law enablers • ASM technology focus: enabling new materials and new device integration roadmaps • Logic scaling • Memory scaling › ALD • ASM ALD Products • Selected applications in Logic, 3D-NAND, DRAM and Emerging Memory › PECVD › Epitaxy › Vertical Furnace ›
Slide 20: PECVD Applications
PECVD APPLICATIONS 3D-NAND Logic and High Speed DRAM Source: TechInsights TEOS BEOL Low-k • High throughput • High throughput • Good wiw uniformity • Good wiw uniformity • High quality • Direct CMP • Stress control • No need for glue layer • Stress control Growing PECVD SAM in 3D-NAND, logic and CIS
Slide 21: Outline
OUTLINE › New Materials and 3D: Moore’s law enablers • ASM technology focus: enabling new materials and new device integration roadmaps • Logic scaling • Memory scaling › ALD • ASM ALD Products • Selected applications in Logic, 3D-NAND, DRAM and Emerging Memory › PECVD › Epitaxy › Vertical Furnace ›
Slide 22: Epi Process Roadmap
EPI PROCESS ROADMAP 7nm 5nm 3nm Channel Undoped Si Undoped Si N Type Undoped Si Undoped Si Undoped Si or HGAA LOGIC 30% SiGe P Type Undoped Si 30% SiGe 30% SiGe or HGAA Source Drain 4% SiP 4-8% SiP / SiAs NSD 40% 4% SiGe SiP 4-8% SiP / SiAs >8% SiP / SiAs >50% SiGe(B) PSD OxideSiGe 40% Cln >50% SiGe
Slide 23: Intrepid ES: Application Library
INTREPID ES: APPLICATION LIBRARY Channel LOGIC • N-type • P-type • Si / SiGe HGAA SiGe / Si gate Si nanowire: Source Drain all around device 8nm radius • NSD Source: imec Source: imec • PSD 4-Fin resistance (Ω/µm) 3D NAND • Channel hole MEMORY (Ω Contact cm) resistivity DRAM Excellent uniformity, •
Slide 24: Intrepid ES: Key Features
INTREPID ES: KEY FEATURES • Low Chamber Volume • Dual Temperature Measurement: Pyrometer / TC • Isothermal Quartz Chamber: Closed Loop Control • Production Proven with High Productivity Intrepid ES delivers isothermal process modules for improved within wafer and wafer-to-wafer performance with the
Slide 25: Trends in Epitaxy: ASM Solutions
TRENDS IN EPITAXY: ASM SOLUTIONS Epi Trends ASM Solutions Logic: Low chamber volume produces predictable laminar 1) Doped Films for S/D Technology Extension gas flow over the wafer for precise doped film control and film interface transitions 2) GAA stack layers with precise interface control (Si
Slide 26: Intrepid ES: Stable Film Properties with Isothermal Quartz Chamber
INTREPID ES: STABLE FILM PROPERTIES WITH ISOTHERMAL QUARTZ CHAMBER Center Thickness Center P% Ave. Thickness Ave. Phosphorus% Data Summary Chamber clean after 1,200 wafer cycles Ave. Center Ave. P% Center P% THK (A) THK (A) Mean 529.3 525.4 4.13 4.02 Min 519.8 518.9 4.10 3.98 Max 539.4 533.3 4.18 4.
Slide 27: Previum: Integrated Surface Pre-Clean for Advanced Logic Applications
PREVIUM: INTEGRATED SURFACE PRE-CLEAN FOR ADVANCED LOGIC APPLICATIONS Previum Previum Next for C Removal H* Si0.44Ge0.56 oxide removal in Previum Radical (FTIR analysis) RPU RPU Optimized pre-clean process to remove SiGeOx In-situ conversion / sublimation for In-situ conversion / sublimation for
Slide 28: Outline
OUTLINE › New Materials and 3D: Moore’s law enablers • ASM technology focus: enabling new materials and new device integration roadmaps • Logic scaling • Memory scaling › ALD • ASM ALD Products • Selected applications in Logic, 3D-NAND, DRAM and Emerging Memory › PECVD › Epitaxy › Vertical Furnace ›
Slide 29: ASM Products: Furnace CVD/Diffusion/Batch ALD
ASM PRODUCTS FURNACE CVD /DIFFUSION /BATCH ALD › A412 PLUS Dual boat/dual reactor system Clustering of different applications between reactors possible – only vertical furnace in the market with this capability Up to 150 product wafer load size › A400 for More than Moore Devices Dual boat/du
Slide 30: A400 / A412 Furnace - Innovation
A400 / A412 FURNACE - INNOVATION Example: Dual reactor batch ALD cluster for IPD 3D High-K capacitors › Integrated Passive Devices consist of inductors, resistors and capacitors embedded in a Silicon Interposer or Wafer Level Package › This technology enables further IC miniaturization, lower cost a
Slide 31: Outline
OUTLINE › New Materials and 3D: Moore’s law enablers • ASM technology focus: enabling new materials and new device integration roadmaps • Logic scaling • Memory scaling › ALD • ASM ALD Products • Selected applications in Logic, 3D-NAND, DRAM and Emerging Memory › PECVD › Epitaxy › Vertical Furnace ›
Slide 32: Device Structure Effect on ALD Technology
DEVICE STRUCTURE EFFECT ON ALD TECHNOLOGY ALD= Plasma ALD (PE ALD) + thermal ALD Thermal ALD Plasma ALD Stoichiometric film Directional nature of regardless of reactants results in non- Source: Semiconductor Engineering directionality uniform composition Source: IMEC › Move to 3D devices necessitate
Slide 33: Introduction
INTRODUCTION › Vertical processing (3DNAND, FINFET, GAA) has added a need for non-directional deposition processes (conformal and selective), which drives increased usage of thermal processes › Continued shrinking gave rise to thicknesses as low as 3Å and thickness uniformity control of 0.1Å! › Cont
Slide 34: However, Costs Are Escalating as Well
HOWEVER, COSTS ARE ESCALATING AS WELL… › Cost of high end fabs are escalating due to cost of equipment (EUV, multiple patterning, novel Intel 10nm Cannon Lake Chip metrology, etc…) >10B transistors at cost of <0.00001 cent per transistor Source: Intel ALD needs to provide the atomic level control at
Slide 35: ALD - Enabler of New Materials - Key Strengths of ALD
ALD - ENABLER OF NEW MATERIALS - KEY STRENGTHS OF ALD Uniformity Step Coverage 25Հ TiN 23.75A 108Å TiN Scale Range 0.25Հ 98% step coverage < 1 Full Range NU% 24.A Interface Control Composition Control Excellent composition Atomically control for engineered ternary alloys interfaces to e.g all ALD op
Slide 36: Growth of ALD in Semi Industry - ALD the New CVD
GROWTH OF ALD IN SEMI INDUSTRY - ALD THE NEW CVD 2003 2008 2013 2018 20+ layers 50+ layers ALD HfO2, ZrO2, ZAZ, ALD HfO2, ZrO2, ZAZ, SiO2, PSG, SiO2, SiN, PSG, BSG… BSG, SiN, Al2O3… 10+ layers ALD TiC, TiN, TaN, ALD TiC, TiN, TaN, Co, FFW, Mo, ALD HfO2, ZrO2 HfAlO, ZrAlO, YSiO, ... ALD TiN, TaN 3-4
Slide 37: Increasing Use of ALD Films
INCREASING USE OF ALD FILMS CHIP DENSITY DRIVING THIN CHALLENGES IN METAL SCALING IN PATTERNING FILMS DRAM AND 3DNAND TECHNOLOGY 40 35 # of ALD Films by Node 30 Film 25 Thickness 20 >250A <250A 15 10 5 0 14/16 nm 10/7 nm Largest area of growth is in thinner films Thermal ALD technology delivers high
Slide 38: Introducing Synergis ALD
INTRODUCING SYNERGIS® ALD › New dual chamber thermal ALD reactor technology evolved from decades of ALD expertise on Pulsar and EmerALD › Leverages industry proven XP8 platform architecture for high productivity solutions for logic and memory applications while maintaining single wafer process contr
Slide 39: Synergis Combines Key ALD Technologies
SYNERGIS® COMBINES KEY ALD TECHNOLOGIES Synergis Single Wafer Synergis® Clustering › Designed to advance performance Process Flexibility of industry ALD toolsets: High Productivity 1. Improve wafer thermal uniformity 2. Enable delivery of low vapor pressure precursors & added process flexibility 3.
Slide 40: Synergis Innovations for Flexibility and Performance
SYNERGIS® INNOVATIONS FOR FLEXIBILITY AND PERFORMANCE THERMAL UNIFORMITY FLEXIBLE PRECURSOR DELIVERY Pulse Pulse Pulse Ternary Source Purge Source Purge Gas Purge schemes A B C x y z 1.0%, 1s 0.2%, 1s Pulse Pulse Co-flow Source Purge Gas Purge schemes A +B C Improved WIWNU performance Ternary and co
Slide 41: Synergis Chamber to Chamber Matching
SYNERGIS® CHAMBER TO CHAMBER MATCHING › Unparalleled chamber to chamber matching for tight wafer to wafer control –irrespective of film thickness | 41
Slide 42: Conformal True ALD Metal Deposition Enabled by Synergis
CONFORMAL TRUE ALD METAL DEPOSITION ENABLED BY SYNERGIS® Top ASM Test Structures Bot *Representative image › Excellent step coverage of pure ALD metal demonstrated on 200X area-enhanced 3DNAND structures | 42
Slide 43: Synergis Enables ALD Productivity for the EUV Era
SYNERGIS® ENABLES ALD PRODUCTIVITY FOR THE EUV ERA Film NU% vs Thickness WPH vs Process Time Synergis vs Spatial Down Time 7 350 6 300 Green 2 Green Time (hours) Synergis 5 Synergis Film Non-uniformity 250 Spatial Wafers per hour Film Non-uniformity Spatial 80% delta in 4 200 maintenance times 3 150
Slide 44: Synergis Addresses the Expanding ALD Application Space
SYNERGIS® ADDRESSES THE EXPANDING ALD APPLICATION SPACE V1 ~1nm metal oxide DX MX M1 ESL V0 Metal oxide hard masks and etch stop layers with tunable etch Low temperature, low-k properties encapsulation and hermetic sealing layers W Barrier layer W ML NT Low resistivity, ultra-thin Low resistivity pu
Slide 45: Synergis ALD: Highest Performance at the Lowest Cost per Wafer
SYNERGIS® ALD: HIGHEST PERFORMANCE AT THE LOWEST COST PER WAFER › Synergis® thermal ALD provides best productivity without sacrificing film performance Reduces cost per wafer for ALD technology by >60% › Flexible platform and architecture to meet needs of sub-7 nm technologies Ability to deposit
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