Applied Materials, Inc. · NASDAQ:AMAT
Applied Materials — 2023 SPIE Advanced Lithography + Patterning Conference
42 slides from Applied Materials's conference presentation, Feb 28, 2023
Slide 1: Applied Materials News from the 2023 SPIE Advanced Lithography + Patterning Conference
Applied Materials News from the 2023 SPIE Advanced Lithography + Patterning Conference February 28, 2023 | Applied Materials External
Slide 2: Forward-Looking Statements and Other Information
Forward-Looking Statements and Other Information This presentation contains forward-looking statements, including those regarding anticipated growth and trends in our businesses and markets, industry outlooks and demand drivers, technology transitions, our market share positions, our development of
Slide 3: Michael Sullivan, Head of Investor Relations
Michael Sullivan Corporate Vice President Head of Investor Relations 3 | Applied Materials External
Slide 4: Semiconductor Wafer Fab Equipment Market Segmentation
Semiconductor Wafer Fab Equipment Market Segmentation By Equipment Type By Device Type By Application NAND DRAM Patterning Steps Transistor Leading-Edge Formation Foundry-Logic ASML TEL Lam Applied KLA Interconnect Formation ICAPS + Specialty Advanced Packaging Lithography Track/Clean/ CVD PVD Epi/
Slide 5: Applied Materials Patterning Served Markets and Share
Applied Materials Patterning Served Markets and Share Industry’s Broadest Portfolio SAM ~29% Share ALD CMP CVD ~23% Etch Metrology ~9% 40% NEW 38% 36% Selective Materials Removal 2013 2017 2021 Thermal * Includes Foundry/Logic and DRAM, Excludes NAND Applied’s patterning SAM has grown at 1.4X the ra
Slide 6: Applied Materials Patterning Served Markets and Share
Applied Materials Patterning Served Markets and Share Industry’s Broadest Portfolio SAM ~29% Share ALD CMP CVD ~23% Etch Metrology ~9% 40% NEW: Pattern Shaping 38% 36% Selective Materials Removal 2013 2017 2021 Thermal * Includes Foundry/Logic and DRAM, Excludes NAND Applied’s patterning SAM has gro
Slide 7: Agenda
AGENDA Steven Sherman New Pattern-Shaping Technology Reduces EUV Steps Keith Wells New CD-SEM Technology Paves the Way to High-NA EUV Q&A 7 | Applied Materials External
Slide 8: Steven Sherman, Advanced Products Group
Steven Sherman Managing Director, GM, Advanced Products Group Semiconductor Products Group 8 | Applied Materials External
Slide 9: Creating Patterns with EUV Lithography
Creating Patterns with EUV Lithography LINES / GRATING Create lines and spaces CUTS Segment lines VIAS Connect layers 9 | Applied Materials External
Slide 10: Pitch Scaling Roadmap
Pitch Scaling Roadmap 10 Minimum tip-to-tip Patterning at line/space pitch g-line scheme /NA / Minimum CD (µm) i-line of ~32nm 1 DUV EUV ~25-30nm 193 (Dry) /NA Single Patterning 193 (Immersion) 0.1 EUV 0.18µm ~15-20nm 90nm Litho Gap EUV Double Patterning 45nm High NA 22nm 0.01 14nm 11nm Min y pitc
Slide 11: EUV Double Patterning Example: Dense Interconnect Lines
EUV Double Patterning Example: Dense Interconnect Lines trench (later filled with metal) metal lines route EUV litho-etch 1 lines/spaces patterned with signals and power within minimum EUV spacing each layer of a chip EUV litho-etch 2 line segments formed with multi-patterning used in the tight tip-
Slide 12: EUV Double Patterning Example: Dense Vias
EUV Double Patterning Example: Dense Vias via (later filled with metal) EUV litho-etch 1 vias patterned with relaxed tip-to-tip spacing vias: connect metal layers EUV litho-etch 2 vias doubled with tight multi-patterning used in the tip-to-tip spacing smallest, most critical layers top view Elliptic
Slide 13: EUV Double Patterning Process Flow
EUV Double Patterning Process Flow Simplified Litho-Etch Litho-Etch (LELE) Process Flow Deposition CMP Lithography Metrology Pattern Clean Metrology Deposition CMP Lithography Metrology Pattern Clean Metrology Wafer Clean Etch Clean Etch Etch EUV LE 1 EUV LE 2 Alignment errors Per-EUV LE energy and
Slide 14: Pattern Shaping Alternative to EUV Double Patterning: Interconnect Lines
Pattern Shaping Alternative to EUV Double Patterning: Interconnect Lines Double Patterning Today’s NEWS: Pattern Shaping EUV 1 Pattern line EUV LE 1 segments with relaxed tip-to-tip spacing Pattern shaping EUV LE 2 reduces tip-to-tip spacing top view Source: Samsung PPACt benefit: delivers the densi
Slide 15: Pattern-Shaping Alternative to EUV Double Patterning: Vias
Pattern-Shaping Alternative to EUV Double Patterning: Vias Double Patterning Today’s NEWS: Pattern Shaping EUV 1 EUV LE 1 Pattern round vias at relaxed EUV spacing Pattern shaping EUV LE 2 creates elliptical vias with tight spacing top view Source: Applied Materials PPACt benefit: delivers high-dens
Slide 16: Introducing Centura Sculpta Patterning System
Introducing Centura® Sculpta® Patterning System A breakthrough innovation for the patterning engineer’s toolkit ✓ Enhances EUV patterns to optimize chip area and cost without EUV double patterning ✓ Reduces patterning complexity to increase yield ✓ Reduces the environmental impact of advanced chipma
Slide 17: Animation: How Pattern Shaping Works
Animation: How Pattern Shaping Works YouTube link: https://youtu.be/GSuTyOMq1Bg 17 | Applied Materials External
Slide 18: Pattern-Shaping Process Flow
Pattern-Shaping Process Flow Simplified Process Flows Deposition CMP Lithography Metrology Pattern Clean Metrology Deposition CMP Lithography Metrology Pattern Clean Metrology Wafer Clean Etch Clean Etch Etch EUV LE 1 EUV LE 2 NEW Deposition CMP Lithography Metrology Pattern Clean Metrology Pattern
Slide 19: Benefits of Pattern Shaping
Benefits of Pattern Shaping Simplified Litho-Etch (LE) Plus Pattern-Shaping Process Flow NEW Deposition CMP Lithography Metrology Pattern Clean Metrology Pattern Wafer Clean Etch Shaping Etch EUV LE No alignment errors Per-layer energy + materials savings Per-layer cost savings >15kWh per wafer ~$25
Slide 20: Breakthrough Innovation for the Patterning Engineer's Toolkit
Breakthrough Innovation for the Patterning Engineer’s Toolkit Press Release “ As Moore’s Law drives us to ever-greater compute performance and density, pattern shaping is proving to be an important new technology that can help reduce manufacturing cost and process complexity and conserve energy and
Slide 21: Breakthrough Innovation for the Patterning Engineer's Toolkit
Breakthrough Innovation for the Patterning Engineer’s Toolkit Press Release “ Three critical issues must be considered when pushing the limits of patterning: tip-to-tip spacing, pattern bridge defects and line edge roughness. As an early development partner on the innovative pattern- shaping technol
Slide 22: Breakthrough Innovation for the Patterning Engineer's Toolkit
Breakthrough Innovation for the Patterning Engineer’s Toolkit Press Release “ Applied Materials’ new Sculpta system is a revolution in patterning that brings an entirely new capability to chipmakers. As the industry keeps pushing the limits of chip scaling, we need breakthroughs like Applied’s patte
Slide 23: Keith Wells, Imaging and Process Control Group
Keith Wells Group Vice President and General Manager Imaging and Process Control Group 23 | Applied Materials External
Slide 24: eBeam Tools: "The Eyes of the Fab"
eBeam Tools: “The Eyes of the Fab” Actionable Segment Applications Purpose Image Insight False SEE Defect Review D to distinguish critical defects from noise, A C SEMVision® E enable root cause analysis B Defect Control Defect DETECT Inspection small, buried and electrical defects PrimeVision® IMEC
Slide 25: CD-SEM: "The Ruler of the Fab"
CD-SEM: “The Ruler of the Fab” High-NA EUV pattern critical dimensions (CD) line pitch 18nm 44nm critical dimension scanning electron microscope (CD-SEM) top view Source: Applied Materials CD-SEM produces precise, sub-nanometer measurements to continuously calibrate lithography process performance 2
Slide 26: CD-SEM: Helping Control Lithography and Etch Patterning Flows
CD-SEM: Helping Control Lithography and Etch Patterning Flows Lithography Module Etch Module Lithography CD-SEM CD-SEM Etch after after etch development CD within CD within inspection inspection spec spec (AEI) (ADI) CD out of spec CD out of spec → rework wafer CD within spec → tune lithography vari
Slide 27: EUV Patterning Requires CD-SEM eBeam Innovations
EUV Patterning Requires CD-SEM eBeam Innovations STANDARD SEM Requirements: Pitch ≥76nm Pitch ≥32nm Pitch ≥24nm top view Process window Process window Process window +/- 1nm +/- 0.7nm +/- 0.5nm SEM precision SEM precision SEM precision 0.1nm 0.07nm 0.05nm 300-500V, 1.4-1.6nm High Resolution SEM ~100
Slide 28: Higher Landing Energy Improves Imaging Resolution
Higher Landing Energy Improves Imaging Resolution Resolution (nm) Landing energy: high energy is used to concentrate the electron beam on better resolution the target area and produce higher required resolution resolution images. Landing Energy (V) 28 | Applied Materials External
Slide 29: Higher Landing Energy Impacts Photoresist
Higher Landing Energy Impacts Photoresist Resist Shrinkage (nm) Landing energy: High eBeam energy acceptable shrinkage increases interaction with the photoresist material, resulting in excess shrinkage and pattern distortion. Landing Energy (V) 29 | Applied Materials External
Slide 30: Acceptable Resolution and Shrinkage Define LE Range
Acceptable Resolution and Shrinkage Define LE Range working LE range Working Landing Energy (LE) Range: Resolution (nm) Resist Shrinkage (nm) CD-SEM landing acceptable shrinkage energies that meet image resolution and shrinkage specifications, enabling lithography required resolution process control
Slide 31: Challenge: Working LE Range Narrows with Lithography Shrink
Challenge: Working LE Range Narrows with Lithography Shrink STANDARD SEM DUV EUV High-NA EUV working LE range Resist Shrinkage Resolution (nm) Landing Energy (V) 31 | Applied Materials External
Slide 32: Introducing VeritySEM 10 CD Metrology
Introducing VeritySEM® 10 CD Metrology Paving the Way to High-NA EUV ✓ Lower landing energy ✓ 2x better resolution ✓ Minimal resist shrinkage ✓ 30% faster production throughput 32 | Applied Materials External
Slide 33: VeritySEM for EUV and High-NA EUV CD Metrology
VeritySEM® 10 for EUV and High-NA EUV CD Metrology STANDARD SEM VERITYSEM® 10 high low high high top view resolution resolution resolution resolution 300-500V, 1.4-1.6nm 300-500V, 1.4-1.6nm High Resolution <300V, SEM 0.8-1.2nm <150V, High 0.8-1.2nm Resolution SEM ≥76nm ~100nm ≥26nm 30-60nm 10-25nm s
Slide 34: Introducing VeritySEM 10 CD Metrology
Introducing VeritySEM® 10 CD Metrology CD Metrology for 3D Structures ✓ GAA – 3x wider back-scattered electron collection enables epitaxy metrology ✓ 3D NAND – 1.5x larger field of view enables next- generation staircase metrology 34 | Applied Materials External
Slide 35: Imaging 3D Structures with Back-scattered Electrons
Imaging 3D Structures with Back-scattered Electrons 3D imaging w/ SE eBeam high- energy cannot image BSE deep trenches deep structure 3D imaging w/ BSE low-energy SE bottom of deep trenches imaged bottom of deep structure BSE: back-scattered electrons top view SE: secondary electrons 35 | Applied Ma
Slide 36: New CD Metrology Steps in GAA
New CD Metrology Steps in GAA VERITYSEM® 10 Selective epitaxy top view is key to GAA nanosheet engineering. VeritySEM® 10 uses BSE technology to measure and characterize the epitaxy process. Ideal Overfilled Underfilled Partial Unmerged Source: Applied Materials 36 | Applied Materials External
Slide 37: New CD Metrology Steps in 3D NAND
New CD Metrology Steps in 3D NAND VERITYSEM® 10 Staircase interconnect architectures increase contact density to 60um reduce die area and via staircase top view cost. VeritySEM® 10 uses a large field of view with high depth of focus to measure the entire staircase structure with detailed depth of fo
Slide 38: Introducing VeritySEM 10 CD Metrology
Introducing VeritySEM® 10 CD Metrology Strong customer pull in logic and memory ✓ Over 30 systems shipped ✓ Logic: DTOR for GAA at multiple customers ✓ DRAM: PTOR for EUV at multiple customers ✓ 3D NAND: DTOR/PTOR for staircase patterning at all leading customers 38 | Applied Materials External
Slide 39: VeritySEM Systems Shipped
<1,300 VeritySEM® Systems Shipped total CD-SEM share foundry/logic CD-SEM share 41% 34% 27% 25% 14% 5% 2013 2017 2021 2023 Source: TechInsights VeritySEM® 4i VeritySEM 5i VeritySEM 6i, 7i VeritySEM 10 BSE High Productivity EUV, High-NA EUV, GAA, 3D NAND 39 | Applied Materials External
Slide 40: High-NA EUV Enablement: VeritySEM Papers at SPIE 2023
High-NA EUV Enablement: VeritySEM® 10 Papers at SPIE 2023 High-NA EUV Title Collaboration Pattern Effect of Stack and High-NA EUV Resist Material on Shrinkage IMEC Unbiased Roughness Measurements for High-NA EUV Characterization IMEC Orientation Measurement on DRAM Contact Hole as an Aberration SK h
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