Asml Holding Nv · EURONEXT:ASML
Asml Holding Nv — UBS Korea Conference 2019
33 slides from Asml Holding Nv's conference presentation, Jun 24, 2019
Slide 1: EUV Update for UBS Korea Conference 2019
Public EUV Update for UBS Korea Conference 2019 Peter Cheang Investors Relation, Asia Seoul, 24 June 2019 Confidential
Slide 2: Speaker Biography
Speaker Biography Public Peter Cheang Slide 2 2 July 2019 Investment Relations Director, Asia ASML Education 1995 Santa Clara University, MBA 1989 UC, Santa Barbara, MSEE 1987 National Taiwan University, BSEE Work Experience 2004 – 2019 Technical Marketing Dir., ASML 2000 – 2004 AVP, Director, Win S
Slide 3: EUV development has progressed over >30 years from Research to HVM insertion
EUV development has progressed over >30 years from Research to HVM insertion Public Slide 3 June 2019 HVM = High Volume Manufacturing EUV consortia 1st lithography ASML starts ASML ships ASML ships ASML ships ASML ships (LLNL, Bell Labs, EUVL research ASET, MIRAI, 2 alpha demo tools: EUVA (Japan) 1s
Slide 4: ASML EUV Lithography product and business opportunity
ASML EUV Lithography product and business opportunity Public Key Messages Slide 4 June 2019 ASML EUV lithography extends our Logic and DRAM customers roadmap by providing lithography resolution improvement, state of the art overlay performance and year on year cost reduction Our customers are prepar
Slide 5: Lithography Process
Public Slide 5 8 November 2018 Lithography Process Confidential
Slide 6: The chip manufacturing loop relies on ASML
The chip manufacturing loop relies on ASML Public Slide 6 June 2019 Deposition Photoresist Exposure Developing Etching Implantation Stripping coating Confidential
Slide 7: Key performance enablers for lithography shrinkage
Key performance enablers for lithography shrinkage Public Slide 7 June 2019 0.65 Rayleigh equation: 0.60 l Resolution = k 1 x 0.55 (min. half pitch) NA NA 0.6 0.50 0.60 0.25 RET i-line l Rayleigh k1 0.45 OPC 0.70 0.85 EUV 0.40 KrF 0.33 0.35 Strong RET 0.80 0.93 0.30 DFM, DET NA ArF 0.25 Double k1 1.
Slide 8: EUV provides patterning simplification compared to multi-patterning immersion
EUV provides patterning simplification compared to multi-patterning immersion Public Slide 8 June 2019 Immersion Multiple Patterning EUV Process Steps 60 CMP 60 Dry Etch # Process steps for 1 patterning step 50 Metrology 40 Lithography 30 Track Deposition 20 34 Clean 10 Hard mask 27 0 LE3 = 3x Litho
Slide 9: Public Slide 9 April 2019
Public Slide 9 April 2019 Confidential
Slide 10: ASML EUV Lithography value for our customer
ASML EUV Lithography value for our customer Public Slide 10 June 2019 Process simplification and improved device performance 15 to 50% cost reduction compared to multi-patterning schemes 3 to 6x cycle time reduction compared to critical multi- patterning layers Best in class overlay performance and
Slide 11: How EUV photon is generated
Public Slide 11 June 2019 How EUV photon is generated Confidential
Slide 12: Creating one single EUV Light pulse
Creating one single Public EUV Light pulse Slide 12 June 2019 Confidential
Slide 13: Creating one single EUV Light pulse
Creating one single Public EUV Light pulse Slide 13 June 2019 Vessel Droplet Tin Generator Catcher CO2 Laser Confidential
Slide 14: Tracking & Hitting the tin droplet twice
Tracking & Hitting the tin droplet twice Public Slide 14 June 2019 Droplet Tin Generator Catcher Confidential
Slide 15: Creating 50,000 pulses per second
Creating 50,000 pulses Public per second Slide 15 June 2019 Vessel Droplet Tin Generator Catcher CO2 Laser Confidential
Slide 16: EUV for HVM: Status and Opportunities
Public Slide 16 June 2019 EUV for HVM: Status and Opportunities Confidential
Slide 17: EUV ramp at our Logic customers has started
EUV ramp at our Logic customers has started with Public production in Logic and DRAM expected in 2019 Slide 17 June 2019 Cumulative exposed 3.2M EUV wafers Total # of wafers exposed 2.0M 1.1M ES Jung, EVP Foundry Seoul October 18th, 2018 0.6M The initial EUV production has started in Samsung's S3 Fa
Slide 18: Our customers are not only talking about EUV
Our customers are not only talking about EUV Public Building significant capacity for EUV systems Slide 18 June 2019 Confidential
Slide 19: EUV estimated demand per fab by market
EUV estimated demand per fab by market Range of layers and corresponding systems per fab1 Public Slide 19 June 2019 Fab Capacity Market EUV layers EUV systems/fab (kwspm2) Logic 45 10 – 20 10 – 20 (7nm – 5nm) DRAM 100 1-6 2 - 10 (16nm -1Anm) Logic EUV capacity: 1 EUV layer requires 1 EUV system for
Slide 20: Expect EUV value increase and cost reduction to bring EUV gross margin to DUV level
Expect EUV value increase and cost reduction to bring Public EUV gross margin to comparable level as DUV Slide 20 June 2019 Increased Customer Value Productivity improvement (availability & wafer per day) System value Overlay and Imaging improvement Process simplification & >40% ~ DUV improved devic
Slide 21: HVM Readiness
Public Slide 21 June 2019 HVM Readiness Confidential
Slide 22: NXE:3400B's availability substantially improved
NXE:3400B’s availability substantially improved Public Growing installed base further improvements planned Slide 22 June 2019 100% 2019 High volume manufacturing target 90% 80% Availability 13wma (%) 70% Average (13wma) 60% 50% 40% 30% 20% 10% USD 0% Maintenance Weeks (2018-2019) 6 systems Data from
Slide 23: EUV infrastructure viable for 7nm and 5nm Logic nodes and DRAM
EUV infrastructure viable for 7nm and 5nm Logic nodes Public and DRAM, improvements on-track for 3nm Slide 23 June 2019 7nm 5nm 3nm Players include Blank Deposition (mask substrate) Inspection Patterning Etch Clean Mask patterning Inspect Defect review Repair Mask pellicles Mask handling Mask Pod Re
Slide 24: EUV scanner defectivity performance and pellicles support manufacturing requirements
EUV scanner defectivity performance and pellicles Public support manufacturing requirements Slide 24 June 2019 DRAM, Logic non critical EUV layers: no Pellicle Critical layers: pellicle Reticle defectivity performance for 7nm logic node 110mm 144mm 2018 2019 Transmission EUV Defectivity level <5 add
Slide 25: EUV Roadmap
Public Slide 25 June 2019 EUV Roadmap Confidential
Slide 26: Our EUV journey so far: > 10 years to develop EUV technology
Our EUV journey so far…. > 10 years to develop EUV Public technology with our customers Slide 26 June 2019 2006 2010 2013 2017 2018-19 ASML ships first full ASML ships first NA ASML ships first NA ASML ships first NA ASML NXE:3400B field EUV research 0.25 development 0.33 development 0.33 production
Slide 27: EUV technology extended for both 0.33NA and 0.55NA
EUV technology extended for both 0.33NA and 0.55NA Public Supporting applications beyond the next decade Slide 27 June 2019 EUV 0.33 platform will be extended to provide state of the art overlay and node to node productivity improvements EUV 0.33 NA 2016 2017 2018 2019 2020 2021 2022 2023 …2025 EUV
Slide 28: In the same way 0.33NA enables 7nm Logic, 0.55NA EUV enables 3nm Logic
In the same way 0.33NA enables 7nm Logic, 0.55NA Public EUV enables 3nm Logic Slide 28 June 2019 Process simplification and improved device performance >> 50% cost reduction compared to multi-patterning schemes 3 to 6x cycle time reduction compared to multi-patterning for critical layers Best in cla
Slide 29: In the same way 0.33NA enables 7nm Logic, 0.55NA EUV enables 3nm Logic
In the same way 0.33NA enables 7nm Logic, 0.55NA Public EUV enables 3nm Logic Slide 29 June 2019 Total patterning cost comparison: ArFi, EUV 0.33, EUV 0.55 Process simplification and improved device performance Non Litho cost Litho cost >> 50% cost reduction compared to multi-patterning schemes 3 to
Slide 30: High NA system design completed, solid progress to support optics development
High NA system design completed, solid progress to Public support optics development and manufacturing Slide 30 June 2019 image removed High NA optics metrology vessels Proto High NA mirror installed in cleanroom @ Zeiss SMT Confidential
Slide 31: ASML EUV Lithography product and business opportunity
ASML EUV Lithography product and business opportunity Public Key Messages Slide 31 June 2019 ASML EUV lithography extends our Logic and DRAM customers roadmap by providing lithography resolution improvement, state of the art overlay performance and year on year cost reduction Our customers are prepa
Slide 32: Forward Looking Statements
Forward Looking Statements Public Slide 32 This document contains statements relating to certain projections, business trends and other matters that are forward-looking, including statements with respect to expected trends and outlook, June 2019 strategy, bookings, expected financial results and tre
Slide 33: Confidential
Confidential