Synopsys, Inc. · NASDAQ:SNPS
Synopsys — Technical Presentation (June 2009)
48 slides from Synopsys's technical presentation, Jun 9, 2009
Slide 1: Faster Design Closure with Congestion Minimization
IC Compiler 2009 Webinar Series Faster Design Closure with Congestion Minimization Design Compiler Graphical & IC Compiler JC Lin, R&D VP Janet Olson, R&D Group Dir June 9th, 2009 ©Synopsys2009 1 IC Compiler 2009 Webinar Series
Slide 2: Welcome!
Welcome! IC Compiler 2009 Webinar Series Congestion Minimization • Previous topics: – Signoff-driven closure – In-design physical verification In-Design Physical IC Signoff- Driven • Upcoming topic: Verification Compiler Closure – In-design rail analysis on 6/25 • Today’s topic: In-Design – Congesti
Slide 3: Presenters Introduction
Welcome! Presenters Introduction Dr. JC Lin R&D VP, Placement and CTS in IC Compiler Janet Olson R&D Group Dir, Design Compiler Graphical ©Synopsys2009 3 IC Compiler 2009 Webinar Series
Slide 4: Agenda
Agenda • Routing congestion and its sources – Congestion causes schedule delays • Design Compiler Graphical and IC Compiler – Best solution for congestion minimization • Traditional congestion minimization flow – Iterations required between synthesis and place & route • Congestion minimization with
Slide 5: Agenda
Agenda • Routing congestion and its sources – Congestion causes schedule delays • Design Compiler Graphical and IC Compiler – Best solution for congestion minimization • Traditional congestion minimization flow – Iterations required between synthesis and place & route • Congestion minimization with
Slide 6: Routing Congestion: A Problem Almost Every IC Designer Faces
Routing Congestion: A Problem Almost Every IC Designer Faces • Congestion occurs when the number of Congestion Map wires going through a routing region exceeds its capacity – To meet timing – To avoid blockages – Due to area constraints To resolve congestion, Place & Route tools need to make intelli
Slide 7: Sources of Routing Congestion
Sources of Routing Congestion • Floorplan – i.e. macro-placement • RTL structures Floorplan-related – i.e. MUX trees • High utilization – i.e. limited room RTL-related ©Synopsys2009 7 IC Compiler 2009 Webinar Series
Slide 8: Congestion Can Be A Major Contributor To Schedule Delays
Congestion Can Be A Major Contributor To Schedule Delays Customer A Customer B 3 months delay 3 months delay RTL modifications RTL modifications 90 nm 65 nm 500K instances 400K instances Consumer Electronics 3G Wireless ©Synopsys2009 8 IC Compiler 2009 Webinar Series
Slide 9: Agenda
Agenda • Routing congestion and its sources – Congestion causes schedule delays • Design Compiler Graphical and IC Compiler – Best solution for congestion minimization • Traditional congestion minimization flow – Iterations required between synthesis and place & route • Congestion minimization with
Slide 10: Galaxy Platform Evolution
Galaxy Platform Evolution From Dataflow to Smart ‘Look Ahead’ Technology Synthesis Synthesis Synthesis Design Signoff Signoff Signoff Planning Design Planning Physical Synthesis Place & Route Place & Route Place & Route 2002 2004 2007 Dataflow Correlation ‘Look Ahead’ ©Synopsys2009 10 IC Compiler 20
Slide 11: Design Compiler Graphical + IC Compiler: Leading Choice for Design Implementation
Design Compiler + IC Compiler Leading Choice for Design Implementation Leading Choice For Synthesis • Best-in-class QoR Design • Correlation w/ layout minimizes congestion Compiler • Automated & complete power synthesis • Faster TAT with in-built test Signoff Leading Choice For Physical Design IC Co
Slide 12: Topographical Technology for Predictability
Design Compiler + IC Compiler Topographical Technology for Predictability Timing & Area Power Test Design Compiler Signoff IC Compiler ©Synopsys2009 12 IC Compiler 2009 Webinar Series
Slide 13: Best Solution for Congestion Minimization
Design Compiler Graphical + IC Compiler Best Solution for Congestion Minimization Accurate prediction of congestion Design Compiler Graphical Early physical visualization Congestion optimization in synthesis MCMM synthesis IC Compiler Shared technology with IC Compiler ©Synopsys2009 13 IC Compi
Slide 14: Agenda
Agenda • Routing congestion and its sources – Congestion causes schedule delays • Design Compiler Graphical and IC Compiler – Best solution for congestion minimization • Traditional congestion minimization flow – Expensive iterations required • Design Compiler Graphical congestion minimization – Fas
Slide 15: Traditional Flow For Handling Congestion
Traditional Flow For Handling Congestion • Focused on timing, power, Synthesis area & test ©Synopsys2009 15 IC Compiler 2009 Webinar Series
Slide 16: Traditional Flow For Handling Congestion
Traditional Flow For Handling Congestion Synthesis Gate level Netlist • P&R tries to resolve Place and Route congestion • Timing driven congestion- High congestion removal discovered • Auto-area-recovery for Congestion high density hot spots minimization • Congestion analysis for techniques floorpla
Slide 17: Traditional Flow For Handling Congestion
Traditional Flow For Handling Congestion Synthesis Gate level Netlist Place and Route High congestion discovered Sometimes P&R succeeds to resolve congestion Congestion minimization techniques ©Synopsys2009 17 IC Compiler 2009 Webinar Series
Slide 18: Traditional Flow For Handling Congestion
Traditional Flow For Handling Congestion Synthesis Gate level Netlist Place and Route High congestion discovered Sometimes P&R does not succeed Congestion minimization techniques ©Synopsys2009 18 IC Compiler 2009 Webinar Series
Slide 19: Convergence Issues with Traditional Flow: Congestion Detected Too Late
Convergence Issues with Traditional Flow 1. Congestion is Detected too Late in the Design Cycle • Design is optimized Synthesis without considering the effect of congestion • WNS: -0.46ns – RTL optimizations are optimistic • Congestion removal in Place & Route P&R leads to tradeoff between timing Qo
Slide 20: Convergence Issues with Traditional Flow: Floorplan Changes
Convergence Issues with Traditional Flow 2. Congestion Removal in P&R May Require FP Changes Congestion with • Congestion removal original channel size in P&R may need floorplan adjustments late in the flow – Schedule gets impacted Congestion with – Possible increase in increased channel size die si
Slide 21: Convergence Issues with Traditional Flow: Unresolvable Congestion
Convergence Issues with Traditional Flow 3. Some Congestion Cannot Be Resolved in P&R ROM • RTL structures can be intrinsically congested – i.e. large MUX trees, ROM – Not trivial to identify in P&R • Intelligent synthesis algorithms needed to free logic from intrinsic congestion ©Synopsys2009 21 IC
Slide 22: Conclusion
Conclusion • Reducing congestion in Synthesis P&R can be expensive • At times, congestion Place & Route cannot be resolved in P&R A solution that considers the effect of congestion in RTL synthesis is needed ©Synopsys2009 22 IC Compiler 2009 Webinar Series
Slide 23: Ideal RTL Synthesis Solution
Ideal RTL Synthesis Solution Tight correlation between synthesis and P&R Shared technology Early visibility into routing congestion Assessing and fixing congestion in synthesis Concurrent congestion optimization Together with timing, area, power and test Better starting point for layout Faster conve
Slide 24: Agenda
Agenda • Routing congestion and its sources – Congestion causes schedule delays • Design Compiler Graphical and IC Compiler – Best solution for congestion minimization • Traditional congestion minimization flow – Iterations required between synthesis and place & route • Design Compiler Graphical con
Slide 25: Congestion Minimization
Design Compiler Graphical Congestion Minimization • Introduction • Key capabilities • Design Compiler Graphical + IC Compiler best practices ©Synopsys2009 25 IC Compiler 2009 Webinar Series
Slide 26: Extending Topographical Technology to Routing Congestion
Design Compiler Graphical Extending Topographical Technology to Routing Congestion • Breakthrough synthesis capabilities – Congestion prediction – Congestion optimization DC Graphical – Physical visualization – MCMM Synthesis • Shares technology with ICC IC Compiler ©Synopsys2009 26 IC Compiler 2009
Slide 27: Delivering Unmatched Productivity
Design Compiler Graphical + IC Compiler Delivering Unmatched Productivity Accurate Congestion Early Physical Congestion Prediction Visualization Optimizations Early visibility into Layout Viewer aids Optimizations for congestion debugging reduced congestion Eliminate Iterations Debug congestion Crea
Slide 28: Utilizing ICC Technology to Address Routing Congestion
Design Compiler Graphical Utilizing ICC Technology to Address Routing Congestion RTL & Constraints Design Compiler Graphical Optimization Congestion Net Model Accuracy Virtual placement is optimization in congestion driven synthesis allows for using global route larger changes Netlist Timing, power,
Slide 29: Congestion Minimization
Design Compiler Graphical Congestion Minimization • Introduction • Key capabilities – Congestion prediction – Physical visualization – Congestion optimizations • Design Compiler Graphical + IC Compiler best practices ©Synopsys2009 29 IC Compiler 2009 Webinar Series
Slide 30: Congestion Prediction – Estimation
Design Compiler Graphical Congestion Prediction – Estimation • Global Route-based congestion estimation • Design partitioned into virtual array of Global Route Cells (GRCs) • Shared Synopsys Global Virtual Grid Route technology Virtual Route i Violation = # of wires ‒ max # allowed wires ©Synopsys20
Slide 31: Congestion Prediction - Reporting
Design Compiler Graphical Congestion Prediction - Reporting • Text based reporting with report_congestion – Similar format as IC Compiler • Provides quick assessment of congestion status Design : Test Version: B-2008.09-SP3 Date : Fri Feb 13 11:38:50 2008 **************************************** Bot
Slide 32: Physical Visualization
Design Compiler Graphical Physical Visualization Layout view Congestion map Congestion due to Floorplan Long path due to macro location Congestion due to RTL Debug timing issues due to Detect and debug sources of layout congestion Early Detection and Debug of Layout Issues ©Synopsys2009 32 IC Comp
Slide 33: Physical Visualization - Congestion Analysis
Design Compiler Graphical Physical Visualization - Congestion Analysis Congestion Map in Layout Viewer 7 6 5 4 3 2 1 0 -20 0 0 ©Synopsys2009 33 IC Compiler 2009 Webinar Series
Slide 34: Physical Visualization - Congestion Analysis
Design Compiler Graphical Physical Visualization - Congestion Analysis Congestion Map in Layout Viewer 7 6 5 4 3 2 1 0 -20 0 0 ©Synopsys2009 34 IC Compiler 2009 Webinar Series
Slide 35: Physical Visualization - Congestion Analysis
Design Compiler Graphical Physical Visualization - Congestion Analysis Congestion Map in Layout Viewer 7 6 5 4 3 2 1 0 -20 0 0 ©Synopsys2009 35 IC Compiler 2009 Webinar Series
Slide 36: Physical Visualization - Congestion Analysis
Design Compiler Graphical Physical Visualization - Congestion Analysis Congestion Map in Layout Viewer 7 6 5 4 3 2 1 0 -20 0 0 ©Synopsys2009 36 IC Compiler 2009 Webinar Series
Slide 37: Congestion Optimizations
Design Compiler Graphical Congestion Optimizations ROM Example 4Kx16 ROM • Optimizes highly connected case (a) 12'h000: z = 16'h991e; logic structures 12'h001: z = 16'hbf94; 12'h002: z = 16'hc0bf; 12'h003: z = 16'h991e; • Creates self-contained sub- 12'h004: z = 16'hbf84; 12'h005: z = 16'hc0cf; stru
Slide 38: DC Graphical + IC Compiler Speed Up Design Closure
DC Graphical + IC Compiler Speed Up Design Closure DC Graphical IC Compiler Congestion Correlated Prediction Congestion Correlated Optimization ©Synopsys2009 38 IC Compiler 2009 Webinar Series
Slide 39: Congestion Optimizations for Adaptive Scan Compression
Design Compiler Graphical Congestion Optimizations for Adaptive Scan Compression • High compression levels can impact congestion – High number of global connections for de/compressor logic – Many scan chains routes required • Adaptive scan compression congestion optimizations – Routing friendly shar
Slide 40: Congestion Optimization for 50X Adaptive Scan
Design Compiler Graphical Congestion Optimization for 50X Adaptive Scan Pre DFT Post DFT Post ICC No Congestion Optimization Pre DFT Post DFT Post ICC Congestion Optimization ©Synopsys2009 40 IC Compiler 2009 Webinar Series
Slide 41: Congestion Optimizations Complement ICC
Design Compiler Graphical Congestion Optimizations Complement ICC Source of Identify/Fix phase Type of optimization congestion RTL structure Identify in DC Graphical Logic based: netlist Fix in DC Graphical structuring, mapping, decomposition Floorplan Identify in DC Graphical Floorplan based: MinCh
Slide 42: Congestion Minimization
Design Compiler Graphical Congestion Minimization • Introduction • Key Capabilities • Design Compiler Graphical + IC Compiler best practices ©Synopsys2009 42 IC Compiler 2009 Webinar Series
Slide 43: Best Practices For Faster Design Convergence
Design Compiler Graphical + IC Compiler Best Practices For Faster Design Convergence • Use same logical and physical libraries – Use same library constraints • Ensure physical library cells exist for all logical library cells – Avoid synthesis with missing designs (black-boxes) • Use the same logica
Slide 44: Consistency Checker to Ensure Convergence
Design Compiler Graphical + IC Compiler Consistency Checker to Ensure Convergence • Correlation issues often due to DC inconsistent settings ICDC Compiler Ultra DC Settings • Automated checking compares settings and highlights differences for: Consistency – Library setup Netlist Checker – Variable/c
Slide 45: Agenda
Agenda • Routing congestion and its sources – Congestion causes schedule delays • Design Compiler Graphical and IC Compiler – Best solution for congestion minimization • Traditional congestion minimization flow – Iterations required between synthesis and place & route • Design Compiler Graphical con
Slide 46: Delivers Faster Turnaround Time & Predictable Schedule
Design Compiler Graphical Delivers Faster Turnaround Time & Predictable Schedule Tight correlation between synthesis and P&R Shared technology Early visibility into routing congestion Assessing and fixing congestion in synthesis Concurrent congestion optimization Together with timing, area, po
Slide 47: Best Solution for Congestion Minimization
Design Compiler Graphical + IC Compiler Best Solution for Congestion Minimization • Congestion can be a major contributor to schedule Design Compiler Graphical delays • Traditional congestion minimization flow may have convergence issues IC Compiler • Design Compiler Graphical addresses congestion d
Slide 48: Predictable Success
Predictable Success ©Synopsys2009 48 IC Compiler 2009 Webinar Series