Formfactor, Inc. · NASDAQ:FORM
Formfactor — Technical Presentation (June 2017)
16 slides from Formfactor's technical presentation, June 2017
Slide 1: Verification of Singulated HBM2 stacks with a KGS Test Cell
Verification of Singulated HBM2 stacks with a KGS Test Cell Dave Armstrong Toshiyuki Kiyokawa Quay Nhin
Slide 2: Paper Discussion Outline
Paper Discussion Outline Industry Need for High Performance HBM Memory – Performance benefits and application drivers – HBM process flow and critical test insertion point – Known good stack die probing key challenges Probe card design challenges: probing on micro-bump at <60um pitch – Design rul
Slide 3: HBM Addresses the Industry's Need for High Performance Memory
HBM Addresses the Industry’s Need for High Performance Memory • Increased Bandwidth • Lower Power Consumption • Higher Density Package – HBM provide higher bandwidth than GDDR5 technology – 40% less power consumption – Smaller form factor with variety of density solutions Source: AMD 8Hi HBM2 [64Gb]
Slide 4: HBM Flow and KGSD Test Challenges
HBM Flow and KGSD Test Challenges memory core Wafer/TSV process Flip Thinning & Bump dicing logic wafer test formation Shipment Flip Dicing & Debonding Wafer/TSV process Flip Thinning stack & Mold & Bump Post-stack Wafer wafer test formation KGS Verification on Test (PSWT) Test Pad @Test Mode μBump
Slide 5: Known-Good-Stack Testing Goals
Known-Good-Stack Testing Goals • Contact all micro-bumps on HBM stacks to allow native mode functional and performance testing on all eight memory channels. • Support at-speed testing > 2.4Gbps. • Supports extreme temperature testing. • Reliable contact to ~4,000 micro-bumps with a pitch of 55um.
Slide 6: Probe Card Design Requirement
Probe Card Design Requirement JEDEC HBM2 Layout Configuration HBM Array Structure • Total TSV Micro Bumps: 3990 − 55μm Micro Bump Pitch (27.5 x 48um staggered) • Total IO Micro Bumps: 1728 • Direct access micro bumps176 • Total Power Supplies: 3 – 1056 • Total ground Micro Bumps: 1030 • Array size
Slide 7: Probe card design challenges
Probe card design challenges Probing on TSV bump at 55um pitch FormFactor Solution – Apollo MF40 MEMs • High speed grid array application • 2Gbps on TSV Micro-bump Challenges: – Design rules for high speed • SI simulation validation • Impedance control from LIF to Tip – ST Trace geometry • Line & Sp
Slide 8: Space Transformation Design Challenges
Space Transformation Design Challenges Small die size, high bump counts • ~4000 traces in ~6x3mm • FFI proprietary ST MLO fan-out design enabler – Pushing the MLO technology limit – Co-develop additional capability for high speed requirement – Line/space and layer count • Impedance control optimizat
Slide 9: FFI MF40 Micro-Bump Probing Characteristics
FFI MF40 Micro-Bump Probing Characteristics
Slide 10: HBM2 Die Micro-bump Probing Results - Ambient
HBM2 Die Micro-bump Probing Results - Ambient • We succeeded in contacting all I/O pins • Ambient scrub mark pictures & result – Contact Time:6sec, Contact : 1 time vs 2 times – Contact Time:600sec, Contact : 1 time vs 2 times The scrub becomes deeper as the number of contacts increases The scrub be
Slide 11: HBM2 Die Micro-bump Probing Results – High Temperature
HBM2 Die Micro-bump Probing Results – High Temperature • We succeeded in contacting all I/O pins • High temperature scrub mark & test result – Contact Time:6sec, Contact : 1 time vs 2 times – Contact Time:600sec, Contact : 1 time vs 2 times The scrub becomes deeper as the temperature becomes higher
Slide 12: Signal Output/Input Performance on HBM2 Die
Signal Output/Input Performance on HBM2 Die • Simulation vs Actual Measurement result @ 2Gbps – The waveform is similar in simulation and actual measurement on HBM2 die – Strong eye-diagram performance correlation Simulation Actual Measurement PRBS T5503 Probe • PRBS signal driver and T5503HS’s comp
Slide 13: Signal Output/Input Performance on HBM2 Die
Signal Output/Input Performance on HBM2 Die • 1ch drive vs 8ch simultaneous drive actual result @ 2Gbps – With data activity on just one memory channel the output data eye width is quite large. – With data activity on all eight memory channels the output data eye shrinks. Shmoo(Dout) 1ch meas. / 1ch
Slide 14: Signal Output/Input at Higher Frequency
Signal Output/Input at Higher Frequency • 1.6GHz/3.2Gbps simulation result – MF40 technology supports operating speed to 3.2Gb/s with additional design rules optimization – Strong simulation versus actual measurement result as validated through ATE at 2Gbps eye-pattern evaluating point T5503HS’s Pro
Slide 15: Benefit Summary
Benefit Summary • Working together as a team Advantest together with FormFactor developed a production worthy tool for confirming Known-Good Memory Stacks with ~4,000 micro- bumps and < 60um bump pitch. • The resulting design exceeded our design goals for probe force and CCC with a wide operational
Slide 16: Acknowledgement
Acknowledgement SK Hynix – Kim Wangki – Seo JaeHyoung FormFactor Inc – Quay Nhin – Hirofumi Nagata – Uyen Nguyen – Todd Swart Advantest – Toshiyuki Kiyokawa – Dave Armstrong – Masayoshi Ichikawa – Tetsuo Shikata – Koji Sakai – Lee Kyungeul – Kim Sangdeuk Author 16