Micron Technology, Inc. · NASDAQ:MU
Micron Technology — Flash Memory Summit 2008
22 slides from Micron Technology's conference presentation, August 2008
Slide 1: ONFI Standards and What They Mean to Designers
ONFI Standards and What They Mean to Designers Michael Abraham mabraham@micron.com Applications Engineering Manager Micron Technology, Inc. Santa Clara, CA USA August 2008 1
Slide 2: NAND Flash Inconsistencies Without ONFI
NAND Flash Inconsistencies Without ONFI Device identification using read ID Array architecture and addressing Command set Timing parameters ECC and endurance Factory-marked bad blocks Device behavior and status Santa Clara, CA USA August 2008 2
Slide 3: Answering Questions
Answering Questions NAND Flash devices must answer basic questions to simplify software development and support: • What is the page size (data • What advanced commands are and spare)? supported? • How many pages per block? • What timing parameters does this device support for normal • How many block
Slide 4: End Result Without ONFI
End Result Without ONFI Qualification Time No Vendor Samples Software/Firmware NAND Driver Product Level Ship New NAND New NAND Updates Testing Testing Standard What are the effects of not having NAND standardization? • Long firmware/software development cycles and updates • Long test/verification
Slide 5: NAND Identification with ONFI
NAND Identification with ONFI Read ID and the parameter page • Device identification • Array architecture and addressing • ECC and block endurance • Timing modes Command set Bad block handling Santa Clara, CA USA August 2008 5
Slide 6: Read ID
Read ID Read ID used today to identify each NAND device Using an address of 20h returns the ONFI signature and indicates that the polled device includes a parameter page CLE WE ALE RE ‘O’ ‘N’ ‘F’ ‘I’ IO0-7 90h 20h 4Fh 4Eh 46h 49h Santa Clara, CA USA August 2008 6
Slide 7: Parameter Page
Parameter Page Parameter page describes Memory Organization Block of the device’s capabilities Parameter Page Number of data bytes per page Sections within the Number of spare bytes per page parameter page Number of pages per block • Revision information Number of blocks per logical unit (LUN) •
Slide 8: Architecture and Addressing
Architecture and Addressing Page 0 Page 0 Page 0 Page 0 Page 1 Page 1 Page 1 Page 1 ONFI uses abstraction because it defines Page P Page P Page P Page P behavior, not an implementation method Block 0 Block 1 Block 0 Block 1 The following ONFI terms are mapped to terms commonly used in NAND Page
Slide 9: Command Set
Command Set Provides consistent, defined st nd Target level Command O/M 1 Cycle 2 Cycle commands commands Read M 00h 30h Copyback Read O 00h 35h Change Read Column M 05h E0h Advanced commands are Read Cache Enhanced O 00h 31h Read Cache O 31h optional (“O”) Read Cache End O 3Fh Block Erase M 60h
Slide 10: Read Cache Enhanced (00-31h)
Read Cache Enhanced (00-31h) Permits reading random pages anywhere on a LUN; important for computing applications Better performance than multi-plane page read since hidden tR < IO time No page address restrictions, unlike multi-plane page read, which requires page address to be the same Com
Slide 11: Read Status Enhanced (78h)
Read Status Enhanced (78h) Reads status on any LUN LUN status register bits • Bits 6 and 5 are generic • Bits 1 and 0 are specific to the selected interleaved address Changes data output between LUNs • Issue 00h command following read status enhanced for data output • Ignores interleaved addre
Slide 12: Get Features (EEh), Set Features (EFh)
Get Features (EEh), Set Features (EFh) Was not highly used in the ONFI 1.0 specification Used in ONFI 2.0 to cover setting of: • Output drive impedance • Interface type (legacy or DDR) • Interface timing mode Includes vendor-specific feature address space to handle the following: • OTP • R/B#
Slide 13: Timing Parameters
Timing Parameters Timing modes represent the timing parameters t t Mode RC WC Unit 0 100 100 ns 1 50 45 ns 2 35 35 ns 3 30 30 ns 4 25 25 ns 5 20 20 ns Supported timing modes are specified in the parameter page Provides consistent timing for controllers Controllers can operate slower than the
Slide 14: An Example: Timing Mode 4
An Example: Timing Mode 4 Each parameter Mode 4 Mode 4 Parameter Min Max Unit Parameter Min Max Unit clearly specified t ADL 70 — ns t RC 25 — ns t t ALH 5 — ns REA — 20 ns t t ALS 10 — ns REH 10 — ns t t AR 10 — ns RHOH 15 — ns All parameters’ edges t t CEA — 25 ns RHW 100 — ns t t CH 5 — ns RH
Slide 15: Factory-Marked Bad Blocks
Factory-Marked Bad Blocks Factory-marked bad blocks are now standardized for SLC and MLC, so both use the same algorithm The block is factory-marked bad if the first byte is 00h (or the first word is 0000h) in the “defect area” in the first or last page of the block Defect area # of data # of
Slide 16: Device Behavior and Status
Device Behavior and Status Behavioral flow shows how the device operates • Target state machine – Handles read ID, read parameter page, and unique ID – Passes LUN operations to the correct LUN (based on address) • LUN state machine – One LUN state machine per LUN in the target – Handles anything t
Slide 17: What are ONFI Shortcomings?
What are ONFI Shortcomings? No interleaved (multi-plane) read page • Coming in ONFI 2.1 Not accepted by all NAND vendors • Would you rather write firmware for eight different NAND vendors or for the equivalent of three? • Micron extends open invitation to the last two NAND vendors to join ONFI
Slide 18: NAND Flash Consistencies After ONFI
NAND Flash Consistencies After ONFI Device identification using the parameter page Array architecture and addressing Command set Timing modes and parameters ECC and endurance Factory-marked bad blocks Device behavior and status Santa Clara, CA USA August 2008 18
Slide 19: Other Concepts in the ONFI Specification
Other Concepts in the ONFI Specification Packaging pinout/ballouts • 48-pin Type-I TSOP • 63-ball BGA • 52-pad LGA with dual x8 interface • 100-ball BGA with dual x8 interface Electrical interface Power-on behavior Discovery and initialization Pin capacitance Santa Clara, CA USA August 200
Slide 20: End Result with ONFI
End Result with ONFI Qualification Time No Vendor Samples Software/Firmware NAND Driver Product Level Ship New NAND New NAND Updates Testing Testing Standard Qualification Time ONFI Vendor Samples Product Level Ship New NAND New NAND Testing What are the effects of ONFI standardization? • Ability
Slide 21: For More Information on ONFI
For More Information on ONFI ONFI specifications are publicly downloadable at http://www.onfi.org/ ONFI membership is available to all; currently 85+ companies participate There are currently no membership dues Santa Clara, CA USA August 2008 21
Slide 22: About Michael Abraham
About Michael Abraham Manager of Micron’s NAND Flash Applications Engineering group B.S. in Computer Engineering from Brigham Young University Micron’s technical representative in ONFI and JEDEC for NAND Flash Key role in defining and standardizing the new high- speed NAND interface within M