Slide 1: ULVAC IR Seminar 2025
ULVAC IR Seminar 2025 Aiming for Further Growth in the Semiconductors and Electronics Field October 3, 2025 Disclaimer regarding forward-looking statements etc. Forward-looking statements Forward-looking statements of the company in this presentation are based on information that was available at th
Slide 2: Growth Strategy
Basic Policy and Vision: New Mid-to-Long-Term Management Plan ~Value-Up Plan~ Growth Strategy Selection and concentration of a business portfolio centered on semiconductors and electronics ⚫ Accelerate focus on Semiconductors and Electronics ⚫ Create new semiconductors and electronics-related busine
Slide 3: Today's Agenda
Today's Agenda 1 Initiatives for Semiconductor Process Expansion 16:05-16:20 Tomoyasu Kondo, Senior Executive Officer, General Manager of Semiconductor Equipment BU 2 New Initiatives in Advanced Packaging 16:20-16:35 Harunori Iwai, Senior Executive Officer Junya Kubo, Sales Department 2 Semiconducto
Slide 4: Initiatives for Semiconductor Process Expansion
Initiatives for Semiconductor Process Expansion Tomoyasu Kondo Senior Executive Officer, General Manager of Semiconductor Equipment BU Copyright© 2025, ULVAC, Inc. All rights reserved 4
Slide 5: Advanced Logic Foundry Technology Roadmap
Advanced Logic Foundry Technology Roadmap » New Mid-to-Long-Term Management Plan Over the six years through FY31/6, the significant structural changes to semiconductor devices will occur » Increased patterning steps and adoption of new materials will expand opportunities for our core PVD deposition
Slide 6: Our Hard Mask Process Expansion and Application to Other Processes
Our Hard Mask Process Expansion and Application to Other Processes New Mid-to-Long-Term Management Technical challenges Plan: Over 2x Growth Spillover to Received orders for over 300 units through technology Other development addressing customer needs Processes Projected Expansion of Equipment Shipm
Slide 7: Our Advanced Semiconductor Development Framework
Our Advanced Semiconductor Development Framework » Strengthening Advanced Semiconductor Device Development: In addition to opening the Technology Center Pyeongtaek (Korea), we have commenced participation in the Imec program in Belgium. We are building a development framework with a forward-looking
Slide 8: Semiconductor & Logic Growth Roadmap
Semiconductor & Logic Growth Roadmap Technology Trends Our Strengths Mid- to Long-Term Our control Strengths Goals Progress in miniaturization Stress Hard Mask PVD+ Introduction of new materials Low-particle film deposition Securing market share through the capture of the Low-temperature film deposi
Slide 9: An Example of Future Technology Development for Advanced Logic
An Example of Future Technology Development for Advanced Logic Example of hard mask applications in Ru DME processes CVD PVD Amorphous Si: Comparison with PVD and CVD Shape distortion during trimming Density, Si purity, low deposition Disadvantageous during pattern temperature, low outgassing CVD PV
Slide 10: Sputtering Technology for Metal Wiring Processes: Logic
Sputtering Technology for Metal Wiring Processes: Logic » Increased opportunities through miniaturization and multilayering of interconnect layers in the logic field ~2024 2025 2026 2027 2028 Conventional Large AP Magnet Target Plasma Wafer Stage Long TS+SIS Longer TS+SIS Magnet Mass production Magn
Slide 11: Semiconductor and Memory Growth Roadmap
Semiconductor and Memory Growth Roadmap Technology Trends Our strengths Mid- to Long-Term Our strengths Goals Progress in miniaturization Low-particle film deposition Maximizing market share Acceleration of 3D structures Stress control in memory processes Introduction of new materials High-density f
Slide 12: Sputtering Technology for Metal Interconnect Processes - Memory
Sputtering Technology for Metal Interconnect Processes - Memory » Increased opportunities due to miniaturization and multilayering of interconnect layers in the memory field, along with the adoption of new structures such as increased total HBM count and CBA. ～2024 2025 2026 2027 2028 Conventional L
Slide 13: Participation in the Imec Program and Future Collaboration
Participation in the Imec Program and Future Collaboration » We have participated in the program of Imec, a leading semiconductor research and development institute based in Belgium. » By leveraging Imec’s expertise and development infrastructure, we aim to accelerate the advancement of next- genera
Slide 14: Growth Strategy: Semiconductor Growth Scenario
Growth Strategy : Semiconductor Growth Scenario » Based on proven hard mask technology and metal film deposition technology, we will increase the number of POR*s for important customers and expand our market share by acquiring new processes, aiming for orders of ¥100 billion or more in FY31/6. Growt
Slide 15: New Initiatives in Advanced Packaging
New Initiatives in Advanced Packaging Harunori Iwai, Senior Executive Officer Junya Kubo, Sales Department 2 Semiconductor and Advanced Electronics Business HQ
Slide 16: Growth Strategy: Growth Scenario for Electronic Devices
Growth Strategy: Growth Scenario for Electronic Devices » We aim to expand to a business scale of over ¥100 billion and further growth mainly through the revitalization of the packaging business and the recovery of power device investments. Growth Strategy Power Packaging Others CS(Electronics) ① Ex
Slide 17: Advanced Packaging / Surface Treatment Technologies
1. Advanced Packaging 2. Surface Treatment Technologies used in Advanced Packaging Copyright© 2025, ULVAC, Inc. All rights reserved 17
Slide 18: Essential Elements for Packaging Required in AI Semiconductors
Essential Elements for Packaging Required in AI Semiconductors Speed Cooling Capacity Durability Mass productivity Copyright© 2025, ULVAC, Inc. All rights reserved 18
Slide 19: The Role and Technological Evolution of Advanced Packaging
The Role and Technological Evolution of Advanced Packaging The Role of Packaging (Fine, Short, High-Density Wiring Connections) Evolution of 2D/3D PackagingTechnologies Conventional Method Advanced Packaging 2.X D 3D Wire Connection Solder Bump Connection Hybrid Bonding Chip B Chip Chip Example: Chi
Slide 20: Our Technologies Utilized in Advanced Semiconductor Packaging
Our Technologies Utilized in Advanced Semiconductor Packaging Desmear Processing for Interposers Electrode formation sputtering Desmear processing for packaging substrates Seed sputtering for packaging substrates Etching for glass processing Etching for fine patterning (optical waveguide formation)
Slide 21: Advanced Packaging / Surface Treatment Technologies
1. Advanced Packaging 2. Surface Treatment Technologies used in Advanced Packaging Copyright© 2025, ULVAC, Inc. All rights reserved 21
Slide 22: Interposer and Key Points for Descum
Interposer and Key Points for Descum MultilayerProcessing Structures in Advanced Packaging Key Points for Multilayer Packaging Flat Surface Poor Connection Good Connection Clean and good adhesion Distorted and dirty Clean and flat Vs. No degradation Efficient transfer of heat and electricity Copyrig
Slide 23: Trends in Connection Technology
Trends in Connection Technology 3 Methods for Connecting Semiconductors: Smaller, Denser, Thinner Wiring Connection Data Transfer Density Thickness 1 1 Slow Bump (Application Example) Board Interconnects, High-Current Applications Micro Bump (Application Example) HBM Stacked Memory Hybrid Bonding (A
Slide 24: Evolution of Connection Methods in HBM
Trends in Connection Technology Evolution of Connection Methods in HBM I. Microbump connection II. Hybrid bonding GPU HBM Connection thickness ≈ Connection thickness ≈ tens of μm several μm or less Interposer Packaging Substrate Copyright© 2025, ULVAC, Inc. All rights reserved 24
Slide 25: Surface Treatment Technologies Used in Bump Connections
Surface treatment technologies used in bump connections Surface treatment to stabilize bump connections Bump connection Surface Treatment Underfilling Chemicals, UV, Plasma, etc. Chip Chip Chip Interposer Interposer Interposer Cleaning Underfill Hydrophilic Treatment As chip and substrate gaps narro
Slide 26: Surface Treatment Technology Used in Bump Connections
Surface Treatment Technology Used in Bump Connections Our Process: Vacuum + Radicals Vacuum Chip Chip Interposer Interposer Carrier wafer/dicing tape Radical: Immediately disappear by highly Vacuum: Maintains radical effectiveness Our Process Equipment reactive collide by prevents unnecessary collis
Slide 27: Hybrid Bonding Applications and Challenges
Connection Technology: Hybrid Bonding Hybrid Bonding Applications and Challenges I. Microbump Connection II. Hybrid Bonding Chip Chip Chip Chip Advantages Challenges • Increased wiring density • High-precision surface treatment and alignment required • Thinner due to bump thickness • Process optimiz
Slide 28: Types of Hybrid Bonding
Activation technology used in hybrid bonding Types of hybrid bonding W to W (Wafer to Wafer) D 2 W (Die to Wafer) Our Focus ・ ・ Wafer Wafer Wafer Die Defective die ・Selection of Known Good Dies (KGD) ・Mounting of multiple chip types Capable of attaching many chips at high speed Good chip sorting and
Slide 29: D2W Bonding
Activation technology used in hybrid bonding D2W Bonding Our Process Wafer Die CMP Dicing Plasma Water Cleaning Transfer Bonding Pressure Thinning Activation Pick Place Annealing An essential process for hybrid bonding Our Strength • Improve substrate surface reaction with using gentle plasma • Dedi
Slide 30: Roles of ULVAC
Interposer and Descum Surface Treatment Processing for Advanced Packaging and the Role of Our Equipment Our Advantage for Bump Connection Our Advantage for Hybrid Bonding Smaller Scale D2W Hydrophilicity Activation Dicing Frame Compatibility Dicing Frame Compatibility Radical Treatment Plasma Contro
Slide 31: Strengths and Future Development of Surface Analysis System
Strengths and Future Development of Surface Analysis System Hirohisa Takahashi Executive Officer, President and Representative Director, ULVAC-PHI, Inc. Takuya Miyayama Senior Manager, Product Strategy Department, ULVAC-PHI, Inc. 社 U Φ 名 \\BUNSEKI_4\backup\LogoData_original\UP\UP_logo_200903\ PNG\ L
Slide 32: ULVAC-PHI Corporate Profile Video
ULVAC-PHI Corporate Profile Video CLICK HERE このプレゼンテーション又は提案は、アルバック・ファイ株式会社の知的財産に基づくものです。 This presentation or proposal is based on the intellectual property of ULVAC-PHI, INC. Copyright© 2025, ULVAC, Inc. All rights reserved COPYRIGHT Ⓒ 2025 ULVAC-PHI, INCORPORATED, All rights reserved. 32
Slide 33: ULVAC-PHI
ULVAC-PHI PHI Gr. • AES Auger Electron Spectroscopy, XPS X-ray Photoelectron Spectroscopy, SIMS Secondary Ion Mass Spectrometry (TOF-SIMS, Q-pole-SIMS) The world‘s only company possessing all three surface analysis techniques (Hardware, Software) • A leading surface analysis instrument manufacturer
Slide 34: ULVAC-PHI History
ULVAC-PHI History May,1969 PHYSICAL ELECTRONICS (PHI) founded by Dr. R. E. Weber of the University of Minnesota • Developed the world‘s first commercial AES surface analysis instrument Subsequently added XPS and SIMS to its product lineup, establishing its position as a surface analysis supplier Fou
Slide 35: ULVAC-PHI Value Proposition and Strengths
ULVAC-PHI Value Proposition Through analytical technologies that "convert the invisible into data and information“, we provide critical data and information that supports customers’ decision-making. Strengths ① Technology featuring high-precision, wide-ranging ② Total coordination of analytical inst
Slide 36: Core Technology: What is Surface Analysis
Core Technology: What is Surface Analysis » Analysis of elemental composition, chemical states, and molecular structure in the surface region at the nanometer scale » A technique that enables material evaluation by combining two-dimensional distribution observation (imaging) and depth profiling anal
Slide 37: Core Technology: Surface Analysis Technology
Core Technology: Surface Analysis Technology Photo XPS (X-ray Photoelectron Spectroscopy) X-rays electron An analytical method that utilizes the photoelectric effect, in which electrons are emitted from a material when it is irradiated with X-rays. The reason why XPS is a surface-sensitive technique
Slide 38: Benefits of Surface Analysis: Thin Film Thickness Measurement
Benefits of surface analysis: thin film thickness measurement Si2p spectrum Si-O Si-O Si PhotoElectron PhotoElectron PhotoElectron Photo X-rays electron intensity intensity intensity Si-O Si Si 0 108 106 104 102 100 98 96 0 108 106 104 102 100 98 96 0 108 106 104 102 100 98 96 Bond Energy Bond Energ
Slide 39: Surface Analysis Techniques: Essential Technologies for Semiconductor Evaluation
Surface analysis techniques: essential technologies for semiconductor evaluation XPS SIMS Non-destructive compositional evaluation Ion Implanter evaluation for source/drain of gate oxide film thickness formation Transistor ✓ Film thickness evaluation of a few nanometers ✓ ppb-level dopant evaluation
Slide 40: Application Fields of Surface Analysis Technology
Application Fields of Surface Analysis Technology Fuel Cell Mineral Polymer Semiconductors Glass Biotechnology Catalyst Pharmaceutical Perovskite Solar cells Display 社 名 \\BUNSEKI_4\backup\LogoData_original\UP\UP_logo_200903\ U Φ PNG\ LVAC-PHI_b_200903.png Lithium-ion batteries Metal ‹#› 40
Slide 41: Challenge from Lab to Fab
Challenge from Lab to Fab » Leveraging experience and achievements in the existing Lab-type model (market share No. 1), we aim to establish a global position in the inspection equipment market by fully introducing "XPS" into the Fab-type model, where the importance of analysis increases due to the a
Slide 42: Differences in Requirements for Analytical Instruments and Inspection Equipment
Differences in Requirements Specifications for Analytical Instruments and Inspection Equipment Analytical Instruments Testing Equipment Takt Time Not specified Required Measurement Target Unknown Known (Materials/Composition) Measurement Method Destructive Non-destructive ‹#› 社 U Φ 名 \\BUNSEKI_4\bac
Slide 43: Business Synergy Between Semiconductors and Electronics BU and ULVAC-PHI
Business Synergy Between Semiconductors and Electronics BU and ULVAC-PHI We are aiming to realize XPS inspection equipment for semiconductor mass production lines by combining both companies' assets ULVAC Semiconductors and ULVAC-PHI Electronics Business Division Surface Analysis Technology (Hardwar
Slide 44: Copyright© 2025, ULVAC, Inc. All rights reserved
Copyright© 2025, ULVAC, Inc. All rights reserved 44