Slide 1: Automotive EMI Demystified: Part 2 – Pursuing an Ideal Power Supply Layout
Automotive EMI Demystified: Part 2 Pursuing an Ideal Power Supply Layout Jens Hedrich Senior FAE, Central Europe December 2018
Slide 2: Jens Hedrich – Senior FAE, Central Europe
Jens Hedrich – Senior FAE, Central Europe 2010 – Present • MPS Senior FAE since 2010, working with industrial and automotive customers on power supply design. • Particular specialty focus on layout and EMC topics, including frequently visiting automotive EMC lab for EVB testing / optimization and im
Slide 3: Agenda
Agenda The Motivation Initial PCB Real Estate Planning How Best to Utilize Each Layer in the PCB Copper Under the Inductor or Not: the Classic Debate EMI-Optimized Schematic and Layout Case Study Frequently Asked Questions About Layout for EMI Open Q&A
Slide 4: Our Motivation: Avoiding This Result
Our Motivation: Avoiding This Result EMC Test Result of a Bad* PCB Without Filter 30V / 7A Sync. Buck Board Optimized for Thermal Performance but not EMC • Large SW area CISPR25 Conducted Test failed by ~50dB • No solid GND plane • Only two Layer • NO EMC Filter
Slide 5: A Much Better Board with EMC Filter
A Much Better Board with EMC Filter OEM Limit Input EMC Filter on Bottom side of PCB Single stage filter with 10µH 5x5x5 and 10µF 1210
Slide 6: A Much, Much Better Board
A Much, Much Better Board 100kHz to 30MHz 9kHz RBW 30MHz to 108MHz 120kHz RBW EVQ4430-00A 480kHz Spread Spectrum 12dBµV OEM Limit 4µV or 80nA@50Ω Large margin Filter on bottom side Two stage filter with small components Learn how to get to this level
Slide 7: Reminder From Last Webinar: Magnetic Antennas
Reminder From Last Webinar: Magnetic Antennas On AC current loops like hot loops, there is still an increased current density at the outside boundary of the loop H-field of current loop Current density is low, but not zero Larger distance d, Wider spread in GND plane d GND plane
Slide 8: Good EMC Design Starts with Initial PCB Real Estate Plan
Good EMC Design Starts with Initial PCB Real Estate Plan Initial PCB Real Estate Plan H- and E-stray fields from DC/DC (simplified) Fields couple into cable and connector DC/DC circuit EMC Filter Components might pick-up noise or Cable will act as get bypassed by E- and H-Fields. antenna EMC Problem
Slide 9: Initial PCB Real Estate Plan: Where to Place the DC/DC?
Initial PCB Real Estate Plan: Where to Place the DC/DC? 𝟏 H- and E-stray fields from DC/DC (simplified) Field reduced with 𝒅𝟐 Less coupling into cable and connector Lower noise on cable DC/DC circuit Move DC/DC away from any connector To avoid direct coupling into cable • EMC filter components…
Slide 10: Coupling From SW-Node Into Other Circuits: Single Side Assembly
Coupling From SW-Node Into Other Circuits: Single Side Assembly No “quiet” place: problem to locate EMC Place a shield filter and connector Below solid Cu-plane (GND) No AC magnetic fields Filter coil Filter coil Cin d <100µm
Slide 11: Single Side Assembly: Placing a Shield
Single Side Assembly : Placing a Shield A Heat-Sink can also act as a Shield Shield Below solid Cu-plane (GND) No AC magnetic fields Filter coil Filter coil D <100µm
Slide 12: How to Utilize a Multi-Layer PCB for Best EMC Performance?
How to Utilize a Multi-Layer PCB for Best EMC Performance? Top Side routing copper High di/dt loop; Clean GND area where DC/DC placed here Vin; HSFET; LSFET; PGND;CIN connector is placed GND GND SW VIN Output side PGND GND area under DC/DC: noisy Inner L1 GND Eddy currents in this area Inner L2: rou
Slide 13: Look at the PCB In 3-Dimensions: Simplified Equivalent Representation
Look at the PCB In 3-Dimensions: Simplified Equivalent Representation Use parasitic elements of the layout to your advantage. A via is a small inductor Cut in GND to separate noisy area from rest High di/dt loop: Vin, HSFET, Clean GND area where LSFET, PGND, CIN connector is placed GND GND SW VIN Ou
Slide 14: Place Copper Under Inductor? Which opinion is right?
Place Copper Under Inductor? Opinion A: Opinion B: “No! AC magnetic field from coil will “Yes! Directly on top side of PCB to create Eddy currents in copper under avoid magnetic fields disturbing inductor. This will reduce effective other layers of the PCB!” inductance and create additional losses!”
Slide 15: Example 1: No Copper Under Coil in all Layers
Example 1: No Copper Under Coil in all Layers Magnetic field lines close around PCB (sketch) Magnetic field from Eddy currents on top of copper, field from Eddy currents Very Bad for EMC cancels original AC magnetic field Eddy currents at edge of hole 4 Layer PCB PCB component ..and edge of Cu-area
Slide 16: Detailed Look on a PCB with a hole, exposed to AC magnetic field
Detailed Look on a PCB with a hole, exposed to AC magnetic field Simplified sketch for illustration! AC-Magnetic field from Hot Loop and Coil These H-fields have opposite direction PCB Layer “Cu” To the original field. AC Magnetic field induces Eddy Currents in Copper Highest current density At edge
Slide 17: Example 2: Copper Under Coil in Layer 4
Example 2: Copper Under Coil in Layer 4 Magnetic field lines from inductor (sketch for illustration only) Magnetic field lines from Eddy currents (sketch); Effective field on top of copper is zero. Eddy currents at edge of hole 4 Layer PCB ..and edge of Cu-area PCB component Out SW L1 L2 L3 Cable L4
Slide 18: Example 3: Copper Under Coil in all Layers
Example 3: Copper Under Coil in all Layers Magnetic field lines from inductor (sketch for illustration only) Magnetic field lines from Eddy currents (sketch). On top of copper area, these fields cancel the original field Eddy currents at edge of hole PCB component 4 Layer PCB ..and edge of Cu-area O
Slide 19: Place GND Copper Under SW-Node?
Place GND Copper Under SW-Node? CON: If copper is placed in the layer directly under SW-node, parasitic capacitance of SW is increased. An AC current will flow across that parasitic capacitor Top side Layout Example EVQ4430 IN SW Out Top GND Inner L1 Inner L2 Bottom SW Ac current SW dV/dt • Parasiti
Slide 20: Buck EMC Optimized Schematic
Buck EMC Optimized Schematic MPQ4430 Family: P2P 1A to 3.5A Two stage Input Filter: Stage L1=1µH; CIN5 and CIN6=1µF 0805* Roughly 19dB attenuation at 450kHz for this stage Stage L2=4.7µH;CIN7&8=4.7µF* Roughly 45dB attenuation for this stage. In total ~64dB more than needed Using L2=2µH would still g
Slide 21: T-EVQ4431-L-00A Top Side
T-EVQ4431-L-00A Top Side Cuts in Top GND to separate noisy PGND from clean GND Two Cout are placed on both sides of coil This shields part of E-Field radiation Symmetric Cin arrangement
Slide 22: T-EVQ4431-L-00A Bottom Side
T-EVQ4431-L-00A Bottom Side To avoid coupling with DC/DC fields, two stage input filter is placed on bottom side. Distance between stages to avoid coupling. Small cap directly at load connector CIN5 and CIN6 for fsw=470kHz: use 0805 1µF Symmetric capacitor arrangement to cancel magnetic field of AC-
Slide 23: T-EVQ4431-L-00A Top Side Detail
T-EVQ4431-L-00A Top Side Detail GND under coil AC Input current loops Noisy input PGND
Slide 24: T-EVQ4431-L-00A Inner Layer 1 Detail
T-EVQ4431-L-00A Inner Layer 1 Detail Ground area for return and eddy currents 70µm distance below Top layer Input GND connection Return current flow Try to avoid holes under hot loops Output GND connection Return current flow Between vias: copper fill This area is larger than Top-Side
Slide 25: T-EVQ4431-L-00A Inner Layer 2 Detail
T-EVQ4431-L-00A Inner Layer 2 Detail Inner L2 has 70µm distance to bottom layer Input current flow Input and Output are routed Output current flow together with return From To source load DC/DC Back to Circuit Back from source load
Slide 26: T-EVQ4431-L-00A Bottom Layer Detail
T-EVQ4431-L-00A Bottom Layer Detail Between vias: copper fill Small cap at pin Solid GND except at input filter and the 555
Slide 27: A Good Design
A Good Design 4.5mm high clip with SW Coil with E-shield
Slide 28: Conducted Emission Test Results
Conducted Emission Test Results EVQ4430-00A 480kHz Spread Spectrum 100kHz to 30MHz 9kHz RBW 30MHz to 108MHz 120kHz RBW 12dBµV OEM Limit Large margin
Slide 29: CE Test (avg) of 3A part with different 6x6mm coils
CE Test (avg) of 3A part with different 6x6mm coils EVQ4430-01A 2MHz Spread Spectrum 100kHz to 30MHz 9kHz RBW 30MHz to 108MHz 120kHz RBW Type of Inductor has huge influence! 6mm height undefined SoW 3mm height defined SoW
Slide 30: Radiated Emissions 30MHz to 200MHz
Radiated Emissions 30MHz to 200MHz Horizontal Average FFT OEM Limit
Slide 31: Some Frequently Asked Questions About Layout for EMC
Some Frequently Asked Questions About Layout for EMC 1. Why Al-Elco at Vin? 2. Is there any difference in output filtering for buck and boost topology? How about 4 switch buck boost? 3. Shall I connect AGND and PGND at the power IC or somewhere else? 4. When do you go for more than 4 layers? 5. Shou
Slide 32: Thank You – Q&A
Thank You – Q&A For more information, contact: automotive@monolithicpower.com Check out our AEC-Q100 Power Management Solutions at MonolithicPower.com
Slide 33: Backup Slides
Backup Slides MES
Slide 34: How About A Two Layer Board?
How About A Two Layer Board? Top Side routing copper High di/dt loop; Very Difficult to get DC/DC placed here Vin; HSFET; LSFET; PGND;CIN Clean GND area where GND connector is placed GND SW VIN Output side PGND GND area under DC/DC: noisy Eddy currents in this area Distance >1.0mm…1.6mm More than10x
Slide 35: Magnetic Antennas
Magnetic Antennas On AC current loops like hot loops, there is still an increased current density at the outside boundary of the loop Current density is low, but not Zero
Slide 36: Magnetic Antennas
Magnetic Antennas Cut around PGND to prevent AC current to disturb to layer Still significant AC current here GND GND That’s the reason you might cut even the GND of the hot loop on the top side. Otherwise there will still be some current GND density left at the edge of your PCB where it will radiat