Slide 1: OCTEON 10 DPU Family
OCTEON 10 DPU Family Accelerating the data infrastructure transformation June 2021
Slide 2: Workloads are shifting to data-centric compute
Workloads are shifting to data-centric compute Application-centric Application-centric Data-centric Data-centric AI, Networking, security, video and storage virtualization © 2021 Marvell. All rights reserved. 2
Slide 3: DPU definition
DPU definition A Data Processing Unit (DPU) Compute is a compute entity that is used to move, process, secure and Accelerators manage data, as it travels or while at rest, to make it available and optimized for application High speed Interfaces © 2021 Marvell. All rights reserved. 3
Slide 4: OCTEON: The original DPU platform
OCTEON: The original DPU platform OCTEON® OCTEON® OCTEON® OCTEON® OCTEON® multicore Fusion TX TX2 10 LiquidIO® 2005 2010 2012 2015 2019 2021 Industry’s 1st DPU First Marvell 6th Generation 7th Generation Arm DPU Marvell DPU Marvell DPU Applications Firewall Cloud Wireless Radios Auto Edge © 2021 Mar
Slide 5: OCTEON 10
Compute leadership Integrated with Arm Neoverse hardware ML N2 cores engine OCTEON 10 Industry Firsts Based on TSMC Integrated 1terabit 5nm process switch VPP hardware Advanced inline acceleration crypto accelerators Compute leadership with industry-leading performance per Watt © 2021 Marvell. All r
Slide 6: OCTEON 10 Platform
NVMe 20M+ IOPs 400G+ Datapath 400+ Gbps IPSEC OCTEON 10 400+ Gbps TLS Platform SPECint Scalable system 100’s 1000+ TOPS performance © 2021 Marvell. All rights reserved. 6
Slide 7: OCTEON platform scalability
OCTEON 10 platform scalability Edge / 5G Enterprise & Core Cloud Scalable features Ethernet port speed 1G 400G Datapath 50G 400G+ Compute SPECint 275 1000+ Security IPSEC/SSL 50G 400G+ Common software © 2021 Marvell. All rights reserved. 7
Slide 8: OCTEON DPU platform
OCTEON DPU platform User Applications Software OCTEON DPU Open Software Platform Optimized Stacks: Virtualization Standard APIs Networking, Storage, and Containers DPDK, SPDK, VPP Security Silicon OCTEON DPU Ethernet / PCIe / Software-enabled Arm cores Memory Controllers Accelerators © 2021 Marvell.
Slide 9: OCTEON innovations
OCTEON 10 innovations ▪ 5nm TSMC process – Enables fanless designs DDR 5 Memory Controllers Arm v9 Arm v9 ▪ First inline DPU ML Engine N2 N2 ………. 64K I / d cache ▪ Hardware VPP acceleration Up to 400GE Ethernet 16 x 50G Ethernet Switch 64K I / d cache 1MB L2 1MB L2 ▪ Inline crypto processor L3 cache
Slide 10: Integrated ML engine
Integrated ML engine Inline ML engine ▪ Best-in-class DPU inferencing ‒ Directly in the data pipeline Shared/System memory ‒ Each ML tile contains private SRAM XBAR/Interconnect ▪ Up to 100x performance vs SW ‒ Supports Int8, FP16 ▪ Use cases ‒ Threat detection ‒ Context-aware service delivery ‒ QoS
Slide 11: VPP hardware acceleration
VPP hardware acceleration Today’s scalar packet processing Packet engine Packet Packet Hardware Hardware packet Header PKT PKT PKT header decision manipulation PKT packet scheduler PKT PKT classification/scheduler logic lookup packet transmit Packet scheduling 1 by 1 OCTEON 10 Vector packet processi
Slide 12: Arm Neoverse N2 advantages
Arm Neoverse N2 advantages ▪ Maximizes performance per watt Arm Neoverse N2 CPU ▪ 3x single-threaded performance ‒ Same software runs faster Core 1 ▪ Lower application latency with 1M L2 cache SVE2 2 Armv9.0-A NEON™ AdvSIMD ▪ Higher performance and scalability 64-bit/32-bit CPU Crypto ‒ SVE2 for hyp
Slide 13: OCTEON Switch integration
OCTEON 10 Switch integration ▪ 1T switch with 16 x 50GE ports ‒ Support from 1GE to 100GE Packet processing pipeline ▪ Feature support Switch control ‒ 256bit MACsec Peripherals ‒ Network overlay for VxLAN/GRE/MPLS Transmit queues/scheduling ‒ Network analytics: sFlow, IPFIX ‒ Flow aware-processing
Slide 14: OCTEON DPU software platform
OCTEON DPU software platform User Applications and Services Optimized Stacks Networking Storage Security Management Virtualization Docker / KNI Hypervisor vSwitch CNI/CSI OpenSSL, TLS, Open framework DPDK / VPP Linux Kernel IPSEC SPDK © 2021 Marvell. All rights reserved. 14
Slide 15: Virtualized Accelerators
Virtualized Accelerators Bare Container VM metal VF driver VF driver VF driver Linux OS Linux netdev VF driver KVM PCIe VF0 (v DPU) VF2 (v DPU) VF3 (v DPU) VF4 (v DPU) Accelerators Accelerators Accelerators Accelerators OCTEON 10 DPU © 2021 Marvell. All rights reserved. 15
Slide 16: Service function chaining
Service function chaining Logical Representation Ingress router NF1 NF2 NF3 Egress router Physical Representation CNF1 CNF APP APP Server vSwitch Ingress Egress classifier CNF2 CNF3 CNF classifier OCTEON 10 vSwitch © 2021 Marvell. All rights reserved. 16
Slide 17: 4G/5G RAN Architectures
4G/5G RAN Architectures Use case Radio Unit Digital Unit Central Unit Disaggregated RAN vRAN Offload O-RAN/vRAN Offload Front Haul Gateway © 2021 Marvell. All rights reserved. 17
Slide 18: Cloud and Datacenter DPU
Cloud and Datacenter DPU Use case Arm compute Datapath Host CPU Up to 400 GE (x86 or Arm) Packet parser Up to 400 GE Application Hardware packet accelerators Network ports Ethernet ▪ Compute: 1000+ SPECint ▪ Storage: 20M+ IOPS ▪ Ethernet ports: Up to 400GE ▪ AI/ML: 100’s TOPS ▪ Datapath: 400G+ ▪ Sec
Slide 19: OCTEON 10 DPU Development Platform
Development Platform OCTEON 10 Compute ▪ OCTEON 10 DPU DPU Development ▪ 24 Neoverse N2 cores ▪ SPECint > 800 Platform Accelerators ▪ inline ML engine ▪ inline IPSec ▪ SSL/TLS ▪ Vector packet processing (VPP) SW ▪ DPDK networking suite for Control, Management and Fast path stacks ▪ SDK with Linux ke
Slide 20: Enterprise router and firewall appliance
Enterprise router and firewall appliance Use case ▪ Scalability from low to high end systems Arm N2 compute Application Datapath ▪ OCTEON 10 compute ‒ Best single threaded performance ▪ Data plane acceleration supports: Packet parser ‒ NG Firewall, IPSec, TLS Hardware packet ‒ L2/L3 forwarding accel
Slide 21: OCTEON platform initial family members
OCTEON 10 platform initial family members Metric CN103XX CN106XX CN106XXS DPU400 N2 Cores Up to 8 Up to 24 Up to 24 Up to 36 Max Frequency 2.5GHz 2.5GHz 2.5GHz 2.5GHz SPECint (2006) >275 >800 >800 >1200 Cache (L2, L3) 8MB, 16MB 24MB, 48MB 24MB, 48MB 36MB, 72MB DDR5 Controllers 2 at 4800MT/s 6 at 520
Slide 22: Marvell: Essential technology, done right
ia MARVELL Essential technology, done right™
Slide 23: Thank You
Thank You