Silvaco Group, Inc. · NASDAQ:SVCO
Silvaco — Technical Presentation (June 2022)
26 slides from Silvaco's technical presentation, Jun 1, 2022
Slide 1: SmartDRC and SmartLVS Physical Verification Tools
SmartDRC and SmartLVS Physical Verification Tools
Slide 2: Contents
Contents • SmartDRC/LVS technology overview • SmartDRC/LVS capabilities • Performance / capacity • Rule coverage • Foundry Support • Summary Copyright │ ©2022 Silvaco, Inc. 2
Slide 3: SmartDRC/LVS Technology Overview
SmartDRC/LVS Technology Overview • Silvaco acquired PolytEDA in Q1 2021. The entire Kiev R&D team has joined SILVACO as the result of acquisition. • Now introducing SmartDRC/LVS and SmartRDE (Run and Debug Environment) generally available since late spring of 2021 • This is the rebranded and improve
Slide 4: Silvaco Custom Design Flow
SmartDRC/LVS Silvaco Custom Design Flow PDK -SPICE Models -Symbols -Pcells -Techfiles -DRC Rules Schematic Process LVS Simulation Setup and Control … Waveform Device SPICE Layout DRC SPICE Analysis Measured Data Parasitic Extraction Parasitic Reduction Reliability Analysis Variation Analysis SPICE M
Slide 5: SmartDRC/LVS Structure
SmartDRC/LVS Structure SmartRDE the GUI cockpit XOR / Text-based Fill layer DRC LVS NVN OPC Diff generation • SmartDRC/LVS has a few executable files: – smartdrc performing DRC, ERC, LVS extraction, fillers, and LVL (XOR and Quick Diff) – smartnvn running LVS comparison – smartrde – GUI cockpit – co
Slide 6: SmartDRC/LVS Under the Hood
SmartDRC/LVS Under the Hood • Innovative layout scanning technology ensuring near- linear scaling and runtime predictability • Combines multiple rules/layers checks • Small and efficient memory footprint • Processing by strips for multi-CPU • Hierarchical processing of cell arrays and macro cells •
Slide 7: Parallel Processing
SmartDRC/LVS Parallel Processing SmartDRC benefits from parallel processing of: • Independent groups of rules (blocks) • Independent parts of layout (strips) Parallel tasks may be run in multi-CPU mode on: • A single multi-core host • Multi-host multi-core platforms • Scalability proven with up to 1
Slide 8: Batch Mode Run
SmartDRC/LVS Batch Mode Run • SmartDRC input – A set of run parameters, so called RCF - run configuration file – The rule file in PWRL - SmartDRC/LVS rule language – Layout file (GDSII, OASIS or OpenAccess) • Command line format – smartdrc drc.rcf <optional commands> – SmartDRC output – Detailed log
Slide 9: Run Configuration File (RCF)
SmartDRC/LVS Run Configuration File (RCF) • Specifies the layout, cell to verify, rule file to use, output file • Allows setting dozens of specific run options and variables • Is the only required command line argument in batch mode A simple RCF may look as follows: TopCell: “sample_top”; // The cel
Slide 10: SmartRDE: Configure Your DRC Run
SmartRDE Configure Your DRC Run • Manage run settings with on-the-fly validity checks • Set optional advanced parameters Copyright │ ©2022 Silvaco, Inc. 10
Slide 11: SmartRDE: View DRC Results
SmartRDE View DRC Results • Use Hierarchical error navigation – • Sort, group and filter DRC violations • Interactively debug with layout editor of choice • Check logs and other reports Copyright │ ©2022 Silvaco, Inc. 11
Slide 12: SmartRDE: Run and View LVS Results
SmartRDE Run and View LVS Results • Manage run settings with on-the-fly validity checks • Start LVS or NVN jobs and monitor their progress • Extraction Errors reports with highlighting • View and debug your LVS results from Match Info tab • Check logs and cells statistics Copyright │ ©2022 Silvaco,
Slide 13: SmartDRC Flows
SmartDRC Flows • Standalone: – Competitive solution against higher cost options • 2nd source, pre-signoff • 3rd Party Flows: – Integrated solution for other vendor flows • Alternative Signoff: – Specific certified foundry/nodes • Silvaco Flows: – Direct replacement in ACD and TCAD Flows to Guardian
Slide 14: SmartDRC Integrations
SmartDRC Integrations EXPERT DRC/LVS • Shipped Integrations : • Launch – Silvaco Gateway and Expert Editors – Native/OA • Run – KLayout Editor – Native • Highlight – Juspertor LayoutEditor – Native/OA – Symica DE – Native/OA • On request GATEWAY – TexEDA LayTools – Native LVS – Cadence Virtuoso – CD
Slide 15: SmartDRC vs. Reference Performance
SmartDRC vs. Reference Performance Using the Google Open Source Caravel SOC example on 130nm Process, Smart Reference 8 CPU DRC was 3X faster than a + Hier mode Competitor (single CPU / Flat) Ref Copyright │ ©2022 Silvaco, Inc. 15
Slide 16: SmartLVS Performance on Big Chips
SmartLVS Performance on Big Chips Test name baseband8_io OPT ROM_512_1024_64 Flexible LCD display LVS Mode Hierarchical Flat Hierarchical + Flat + Blackbox (mixed) Process 250 nm 130 nm logic rules Special rules Chip size, um 5004.1 x 9954.1 1432 x 1074 132236.110 by 161550.000 Number of devices 304
Slide 17: SmartLVL Performance Glass Substrate
SmartLVL Performance (1.5m x 2m) Glass Substrate Peak Elapsed Run Time # of CPUs memory hh:mm:ss MB 2 4:48:43 664 4 2:46:54 668 8 1:27:41 662 Copyright │ ©2022 Silvaco, Inc. 17
Slide 18: PWRL Rule Language
PWRL Rule Language • PWRL (pronounced Power-L) • Rich set of checks and operations • Flexible due to preprocessing tools like variables, conditionals, macros, and includes • Easy to learn and use • Allows for full or partial rules encryption (Silvaco’s encryption library) • Compile Only mode of Smar
Slide 19: PWRL Examples (DRC)
PWRL Examples 1 (DRC) Simple spacing rules: Edge operations: w2bs {//@Minimum SUB_E width ... 0.5 pmve_ex61 = $coincident_outside_edge tmp_1 = sub - dti_all; pmve_psd pmve_s2; $width tmp_1 < 0.5 $singular;// tmp_1 = $expand_edge pmve_ex61 $outside_by } 1.09; s1bs {//@Minimum SUB spacing/notch ... 2.
Slide 20: PWRL Examples (LVS)
PWRL Examples 2 (LVS) • Connectivity: – $connect m2trm m1trm csf_m1 $by via1 ; – $connect csf_m2 m1trm csf_m1 $by via1 ; – $sconnect ndiff ntap ; – $sconnect ptap bulk ; • Text labels: – $attach met1_text m1trm ; – $attach met2_text m2trm ; – rpp1_3 = $with_text "rpp1_3" rpp1 polylabel_txt ; • Devic
Slide 21: PWRL vs. SVRF: Very Similar, Yet Different
PWRL vs. SVRF Very Similar, Yet Different • You cannot get PWRL from SVRF by mere substitution of keywords • SVRF: arbitrary order of commands in the rule files, PWRL: strict order • No direct SVRF equivalents, e.g., for PWRL's block or $via_enclosure • Likewise, no direct PWRL equivalents for some
Slide 22: PWRL Pre-Advanced Nodes
PWRL Pre-Advanced Nodes Copyright │ ©2022 Silvaco, Inc. 22
Slide 23: Foundry Support: Rule Decks
Foundry Support Rule Decks • As PolytEDA – 10 Signoff decks from 40nm to 500nm from 6 foundries • Working to recertify these signoff decks • As Silvaco >70 processes supported from 10+ foundries – 3 Signoff decks (XFAB), 5 in process (XFAB, Tower, IHP) – Rule decks starting at 40nm – Expect to be ab
Slide 24: Rule Deck Support
Rule Deck Support Our Rule Deck focus is: • 40nm and above – Should be able to handle 28nm – Below 28nm, colorization and FinFET extensions are required • Roadmap plans • Tier 2 Foundries – AMS, Dongbu, IHP, On-Semi, SkyWater, Tower, Vanguard, Xfab, Others TBD • Prefer to do all/most processes of a
Slide 25: Available Decks
Available Decks Node Foundry Process Node (nm) Foundry Process Node (nm) Foundry Process (nm) Tower (new) TPS65RF 65 UMC UMC-65LL 65 AMS AC18 180 Tower (new) SBL13PC 130 UMC UMC-130MM 130 AMS AH18 180 Tower (ITAR) CA13SAV 130 UMC UMC-018MMRF 180 AMS S35 350 Tower (new) CA13SC 130 Vanguard VT015CBSP0
Slide 26: Summary
Summary SmartDRC/LVS with SmartRDE • Silvaco believes we have a great solution for customers at 28nm and above • Cost-efficient • Competitive performance • Foundry-proven • Customer-proven • We would like the opportunity to solve your verification needs • For foundries/processes not currently suppor