Synopsys, Inc. · NASDAQ:SNPS
Synopsys — Technical Presentation (2018)
20 slides from Synopsys's technical presentation, 2018
Slide 1: Novel Full-chip Verification Methodologies for Domain-crossing and Transient Latch-up Damage Prevention
2018 International ESD Workshop Novel Full-chip Verification Methodologies for Domain-crossing and Transient Latch-up Damage Prevention David Klein, (Synaptics), Yuri Feinberg, Simon Young, (Silicon Frontline Technology)
Slide 2: Biography
Biography When Mr. David Klein received a M.S. degree in Electrical Engineering from Washington State University in 1995, he never intended to get into ESD research and design. He joined Integrated Device Technology as a mixed signal engineer, but the first project he was assigned to failed during
Slide 3: Abstract
Abstract As technologies shrink resulting in lower junction and oxide breakdown voltage levels, internal circuits become more susceptible to damage from IEC-61000-4-2 system level stress. This internal damage can result from oxide break down or transient latch-up triggered by the IEC stress. Two ana
Slide 4: CDM Analysis Tool
CDM Analysis Tool Why use a CDM tool to analyze IEC-induced failure? IEC pulse has two peaks. The 1st peak has a very fast rise time and high current level as shown in Figure 1 Figure 1. Ideal 8kV IEC-61000-4-2 waveform. The first peak’s electrical characteristics are very similar to a CDM puls
Slide 5: CDM Analysis Tool
CDM Analysis Tool Why use a CDM tool to analyze IEC-induced failure? (cont.) Due to high displacement current levels, the 1st peak in IEC pulse is usually the cause of damage to internal circuits like level shifters and driver/receiver (D/R) pairs Our test case passed 1kV CDM but failed 8kV IEC
Slide 6: CDM Analysis Tool
CDM Analysis Tool Introduction of CDM Analysis Tool DC simulation Runs on the full chip level Calculates and lists ground path resistance for every driver/receiver (D/R) pair Similar to a FDCDM test, it simulates discharge on each package pin Gate oxide damage is more common for receivers of
Slide 7: CDM Analysis Tool
CDM Analysis Tool VSS(inv) + X - VSS(inv) VSS(nand2) + + + Resistive GND network with distributed charge + + + + + + + pad pad pad pad pad pad Figure 2. Conceptual illustration of a D/R pair. The bottom NMOS in the NAND2 will have the voltage across its gate oxide, VGS, determined by the current thr
Slide 8: CDM Analysis Tool
CDM Analysis Tool Charge distribution mechanism Charge is induced equally over the chip on the metals or guard ring. Wire-bond/COG packages have charge distributed on upper level metals Flip-chip packages have charges distributed on substrate contacts (guard rings) The area of the metals o
Slide 9: Study Case of CDM simulation
Study Case of CDM simulation Failure Case Failure only occurred during IEC-61000-4-2 contact discharge to the ground plane of the fPCB that was part of a face down display module. The damage was to the integrated touch and display driver ASIC which was fully operational during the test ASIC le
Slide 10: Study Case of CDM simulation
Study Case of CDM simulation Figure 3 Left: Photoemission at the failure locations in the receivers. During this capture, the ASIC is powered up and operational with only the functionality of this block compromised. Please note: After IEC stress, a random distribution of the devices in the circled a
Slide 11: Study Case of CDM simulation
Study Case of CDM simulation Figure 4. Core VDD inb in_buffered Signal from core Analog GND Left: List of overstressed D/R pairs. The circled black arrow highlights the path from driver to receiver. Right: The schematic with discharge path of the D/R pair 2018 International ESD Workshop Page 11
Slide 12: Study Case of CDM simulation
Study Case of CDM simulation Analysis and Improvement In this design, the driver and receiver use the same analog ground. There is relatively high resistance between the core ground and the analog ground at this location allowing for large core VDD to analog ground voltage buildup. Inspection of
Slide 13: Study Case of CDM simulation
Study Case of CDM simulation Anti-parallel diodes between core GND and AGND Figure 5. Simulation results with the fix (adding new anti-parallel diode) 2018 International ESD Workshop Page 13
Slide 14: Guard Ring Analysis Tool
Guard Ring Analysis Tool Introduction of Guard Ring Analysis Tool DC simulation Generates Rmap from each power pad to its guard rings Calculates the resistance from a user defined sampling resolution on the guard ring to its corresponding power pad. For example, p2p_rmap_multinets net_patter
Slide 15: Study Case of Guard Ring simulation
Study Case of Guard Ring simulation Guard Ring Metal 1 A B Metal 2 H C Metal 3 G F E D Power PAD Figure 6. Conceptual illustration of the guard ring analysis. The tool calculates the resistance from each sample point (A-H) to the power pads. 2018 International ESD Workshop Page 15
Slide 16: Study Case of Guard Ring simulation
Study Case of Guard Ring simulation Failure Case During IEC-61000-4-2 contact discharge to the ground plane of an fPCB that was part of a face down display module, damage occurred to an internal circuit that had been used in multiple earlier designs without issue. The damage looked like latch-up
Slide 17: Study Case of Guard Ring simulation
Study Case of Guard Ring simulation Figure 7. Rmap of AGND and VSP supply networks along with damage locations in red circles 2018 International ESD Workshop Page 17
Slide 18: Study Case of Guard Ring simulation
Study Case of Guard Ring simulation Resistance heat map Log10(1+ Resistance) heat map ESD Diodes ESD Diodes VSP AGND VSP AGND VSP NMOS and PMOS capacitor array with poor internal guard rings Figure 8. Zoomed in and annotated screen shots of Rmap for AGND and VSP supply networks next to damage locati
Slide 19: Conclusion
Conclusion In this presentation, we successfully used the CDM analysis tool from SFT to assist in debugging IEC induced failures in D/R pairs. The tool is capable of highlighting high ground resistance in the D/R pairs and the results match the failure analysis results. This makes the tool very usef
Slide 20: References
References [1] Melanie Etherton, Scott Ruth, James W. Miller, et al, “A New Full-Chip Verification Methodology to Prevent CDM Oxide Failures,” 2015 ESD Symposium, Reno, NV, USA. 2018 International ESD Workshop Page 20