Applied Materials, Inc. · NASDAQ:AMAT
Applied Materials — 2024 SEMICON West Technology Breakfast
91 slides from Applied Materials's conference presentation, Jul 9, 2024
Slide 1: 2024 SEMICON West Technology Breakfast
2024 SEMICON WEST TECHNOLOGY BREAKFAST
Slide 2: Forward-Looking Statements
Forward-Looking Statements This presentation contains forward-looking statements, including those regarding anticipated growth and trends in our businesses and markets, industry outlooks and demand drivers, technology transitions, our business and financial performance and market share positions, ou
Slide 3: Race for AI Leadership Fueled by Materials Engineering
RACE FOR AI LEADERSHIP Fueled by Materials Engineering Michael Sullivan Corporate Vice President JULY 9, 2024
Slide 4: 2016 Analyst Day
2016 ANALYST DAY | September 21, 2016 4 | Applied Materials External
Slide 5: 2017 Analyst Day
2017 ANALYST DAY | September 27, 2017 5 | Applied Materials External
Slide 6: AI Design Forum 2018
AI Design Forum™ 2018 Tuesday, July 10, Yerba Buena Theater, SF Bill Dally, Ph.D. Chief Scientist NVIDIA 6 | Applied Materials External
Slide 7: AI Design Forum 2018
AI Design Forum™ 2018 Tuesday, July 10, Yerba Buena Theater, SF Gary Dickerson CEO Applied Materials 7 | Applied Materials External
Slide 8: AI Design Forum 2019
AI Design Forum™ 2019 Tuesday, July 9, Yerba Buena Theater, SF Let's push from Google and the other AI people down towards materials. And let's push from materials and devices back up. I'd love to learn about your field and teach you about my field so we can build those solutions and the next genera
Slide 9: Agenda
AGENDA 7:35 Prabu Raja, Ph.D. 8:20 Device Inflection Expert Panel Race for AI Leadership » Mehul Naik, Ph.D. Transistors and Wiring Fueled by Materials Engineering » Sony Varghese, Ph.D. DRAM » Jinho An, Ph.D. High-Bandwidth Memory 7:55 Mark Fuselier » Sarah Wozny, Ph.D. Heterogeneous Integration Po
Slide 10: Race for AI Leadership Fueled by Materials Engineering
RACE FOR AI LEADERSHIP Fueled by Materials Engineering Prabu Raja, Ph.D. President, Semiconductor Products Group JULY 9, 2024
Slide 11: Tectonic Shifts in Technology are Built on Semiconductors
Tectonic Shifts in Technology are Built on Semiconductors DATA CENTER AI EDGE AI and IOT EV and AV RENEWABLE ENERGY $8T $2T $1.5T $4.5T by 20301 by 20302 by 20303 by 20304 Source: 1 Gartner, 2 Fortune & Skyquest , 3 Yole, assumes 40% EV/AV L2+, 4 IEA AI is the biggest inflection of our lifetimes 11
Slide 12: Growth in AI Driving Increasing Energy Consumption
Growth in AI Driving Increasing Energy Consumption GPT-2 GPT-3 GPT-4 (2018) (2020) (2023) Compute for Model 1X 100X 10,000X Training (FLOPs) Energy Consumption1 1X 20X 250X Number of Chips2 1X 20X 100X AI to grow to 8% of US electricity demand3 by 2030 Source: Generative AI 2024 - Impact on Processo
Slide 13: Industry Focused on Accelerating Energy-Efficient Performance
Industry Focused on Accelerating Energy-Efficient Performance >100X 30X Performance/Watt (Log Scale) MI300 Over the next decade, we must think of energy MI250 efficiency as the most important challenge.” Lisa Su, Ph.D. CEO, AMD 2014 2016 2018 2020 2022 2024 2026 2030 Source: https://spectrum.ieee.or
Slide 14: Key Architecture Inflections Fueling the AI Race
Key Architecture Inflections Fueling the AI Race Leading-edge logic High-performance DRAM High-bandwidth memory Advanced packaging 14 | Applied Materials External
Slide 15: All Architecture Inflections Are Becoming 3D
All Architecture Inflections Are Becoming 3D High-Performance Logic Compute Memory Advanced Packaging GAA Backside Vertical Transistor High Bandwidth Heterogenous 3D DRAM Memory Integration Transistor Power DRAM GAA: gate-all-around Race to bring new architectures to market and secure AI leadership
Slide 16: 3D Inflections Have Increasing Process Complexity
3D Inflections Have Increasing Process Complexity FinFET GAA 33% improvement in energy efficiency Source: TSMC GAA: gate-all-around FET: field-effect-transistor New materials, selective deposition and removal, and process step interactions 16 | Applied Materials External
Slide 17: Process Complexity
Silicon nanosheet VIEW OF PROCESS Gate oxide COMPLEXITY (GAA Transistor) In just ~10nm between nanosheets: Metal gate » >5 distinct materials » 1–2nm per layer of material Engineered with angstrom-level precision across more than ten trillion transistors at a time 17 | Applied Materials External
Slide 18: GAA Transistor: 4 Major Modules
GAA Transistor: 4 Major Modules 4 Contact 3 Gate 2 Source / Drain 1 Nanosheet >2,000 >500 PROCESS STEPS FOR GAA TRANSISTOR PER WAFER FORMATION GAA: gate-all-around 18 | Applied Materials External
Slide 19: GAA Contact Engineering
GAA Contact Engineering metal dielectric metal Contact Resistance spacer metal gate stack ~1.5X Si nanosheet channel source drain 3nm 2nm Shrinking the contact area increases contact resistance GAA: gate-all-around 19 | Applied Materials External
Slide 20: GAA Transistor Contact: Increasing Process Complexity
GAA Transistor Contact | Example of Increasing Process Complexity Clean Deposition hardmask MODULE ~20 STEPS 2 co-optimized processes, 2 integrated solutions Deposition patterning film Track photoresist metal metal Co-optimized etch and dielectric Lithography trench pattern deposition processes Lith
Slide 21: Applied's Unique Connected Materials Engineering Portfolio
Applied’s Unique Connected Materials Engineering Portfolio BROADEST CAPABILITIES UNIQUE COMBINATIONS Applied Competitors Unit Process Tools ALD ✓ ✓ ✓ ✓ Cleans ✓ ✓ Co-optimized Solutions CMP ✓ CVD ✓ ✓ ✓ ✓ ✓ ECD ✓ ✓ Integrated Materials Solutions Epitaxy ✓ ✓ (IMS™) Etch ✓ ✓ ✓ ✓ Furnace ✓ AIx™ Implant
Slide 22: GAA Contact: Integration Improves Resistance, Speed, Power
GAA Contact | Integration Improves Resistance, Speed, Power Clean Deposition hardmask Deposition patterning film Track photoresist Contact Resistance Co-optimized etch and Lithography trench pattern Silicon Interface deposition processes Lithography contact pattern Etch patterning film open Etch har
Slide 23: Demand for Integrated Solutions Growing with Device Complexity
Demand for Integrated Solutions Growing with Device Complexity Complexity Grows Applied’s Integrated Step Growth NODE ~TOTAL STEPS >140 ~125 2nm >2,100 3nm 1,900 ~75 5nm 1,800 7nm 1,500 16/14nm 1,000 28nm 750 7nm 3nm 2nm 23 | Applied Materials External
Slide 24: Applied's Playbook for Accelerating Connectivity
Applied’s Playbook for Accelerating Connectivity 1 2 3 Connect our unique Connect Applied’s Connect with customers portfolio of materials innovators to accelerate and partners, earlier and engineering products invention of novel deeper, to co-innovate solutions: new the industry roadmap organization
Slide 25: Connecting Applied's Unique Materials Engineering Portfolio
2013 1 Connecting Applied’s Unique Materials Engineering Portfolio PVD ALD Producer™ CVD CVD PVD PVD Reflow Reflow ALD ALD Treat ALD Centris™ Sym3™ Etch Endura™ PVD Example: Endura™ IMS™ Integrated Materials Solution Unit Processes Co-optimized Processes Integrated Processes One technology Two or mo
Slide 26: Connecting Applied's Innovators to Invent Novel Solutions
2018 2 Connecting Applied’s Innovators to Invent Novel Solutions NEW ORGANIZATIONS ACCELERATORS Integrated Materials Solutions (IMS™) Maydan Technology Center ICAPS* Materials Engineering Heterogenous Integration (HI) Technology Accelerator Actionable Insight Accelerator (AIx™) Advanced Packaging Sy
Slide 27: Connecting Partners to Accelerate the Industry Roadmap
2023 3 Connecting Partners to Accelerate the Industry Roadmap “UNIVERSITY ENVIRONMENT” EQUIPMENT COMPANY CHIPMAKER Commercial Technology Technology Commercial Proof of Equipment & Integrated into Integrated into Chip Idea Concept Process Module Device 5 – 7 YEARS 2 – 3 YEARS 1 – 2 YEARS 1 – 2 YEARS
Slide 28: Samsung Electronics collaboration quote
Modern semiconductor technology cannot be successfully developed by a single company. Therefore, Samsung Electronics is conducting various collaborations with Applied Materials across all areas of future technology through process development to develop next-generation memory semiconductors, includi
Slide 29: Fueling the Race for AI Leadership
Fueling the Race for AI Leadership AI is the Addressed by New collaboration biggest inflection major architecture playbook will of our lifetimes inflections accelerate new AI architectures Limited by compute Enabled by Applied’s unique energy-efficiency and connected materials engineering portfolio
Slide 30: Agenda
AGENDA 7:35 Prabu Raja, Ph.D. 8:20 Device Inflection Expert Panel Race for AI Leadership » Mehul Naik, Ph.D. Transistors and Wiring Fueled by Materials Engineering » Sony Varghese, Ph.D. DRAM » Jinho An, Ph.D. High-Bandwidth Memory 7:55 Mark Fuselier, AMD » Sarah Wozny, Ph.D. Heterogeneous Integrati
Slide 31: Power and Performance in the AI Era
Power and Performance in the AI Era Mark Fuselier Senior Vice President, Technology and Product Engineering AMD JULY 9, 2024
Slide 32: Enabling the Device Inflections
Enabling the Device Inflections Mukund Srinivasan, Ph.D. Vice President and General Manager, Semiconductor Products Group JULY 9, 2024
Slide 33: Call to Action
CALL TO ACTION 1. Logic: More transistors operating at lower power 2. Memory: Higher capacity and bandwidth, lower latency 3. Packaging: Tightly integrated logic, memory and I/O to increase energy-efficient performance 33 | Applied Materials External
Slide 34: Agenda
AGENDA 7:35 Prabu Raja, Ph.D. 8:20 Device Inflection Expert Panel Race for AI Leadership » Mehul Naik, Ph.D. Transistors and Wiring Fueled by Materials Engineering » Sony Varghese, Ph.D. DRAM » Jinho An, Ph.D. High-Bandwidth Memory 7:55 Mark Fuselier » Sarah Wozny, Ph.D. Heterogeneous Integration Po
Slide 35: Driving Energy-Efficient Performance: Improves 3X Every Years
Driving Energy-Efficient Performance: Improves 3X Every 2 Years Energy-Efficient Performance Drivers Include: Projected 100 New 1. New transistors and Transistor materials GAA 1 EEP (1/(fJ∙psec)) 2. EUV lithography plus design-technology 0.01 co-optimization (DTCO) DTCO Backside 3. Circuit and archi
Slide 36: DTCO: Another Way to Increase Transistors per Chip
DTCO: Another Way to Increase Transistors per Chip Contribution to Logic Density Scaling Intrinsic Scaling (Litho) DTCO Intrinsic Scaling DTCO N N N+1 N+1 >50% >40% >25% 1% 16nm 10nm 7nm 5nm 3nm Source: M. Liu/TSMC, ISSCC 2021 DTCO: Design Technology Co-Optimization DTCO is enabled by materials engi
Slide 37: STCO: Improves System Energy Efficiency by Orders of Magnitude
STCO: Improves System Energy Efficiency by Orders of Magnitude GPU GPU Bump Microbumps TSV Hybrid Bonding Packaging Interconnect Scaling I/O Density 102 103 104 104 to 106 (I/O per mm2) Energy 1.5 0.5 0.1 0.05 (picoJ per bit) STCO: system technology co-optimization STCO is enabled by materials engin
Slide 38: Co-Innovating with Our Partners: The Global EPIC Platform
Co-Innovating with Our Partners: The Global EPIC Platform Maydan Technology Center, Sunnyvale CA META Center, Albany NY Advanced Packaging Dev. Center, Singapore EPIC Center™ (Planned), Sunnyvale CA Deploying our broad, deep and connected portfolio of materials engineering solutions to support high-
Slide 39: Micron collaboration quote
AI workloads demand massive compute memory capacity and bandwidth. To meet these demands, Micron is adopting novel manufacturing technologies for new DRAM transistor architectures and advanced packaging for higher bandwidth. With Applied Materials and its partners, we can rapidly access an expansive
Slide 40: Device Inflection Expert Panel
Device Inflection Expert Panel Mehul Naik, Ph.D. Sony Varghese, Ph.D. Jinho An, Ph.D. Sarah Wozny, Ph.D. Vice President of Sr Director of Technical Account Technologist Director, Semiconductor Technology, Marketing, Semiconductor Director, Semiconductor Products Group Semiconductor Products Products
Slide 41: Transistors and Wiring
Transistors and Wiring Mehul Naik, Ph.D. Vice President of Technology, Semiconductor Products Group JULY 9, 2024
Slide 42: The Transistor Roadmap
The Transistor Roadmap Planar FinFET GAA FET: field effect transistor; GAA: gate-all-around 42 | Applied Materials External
Slide 43: Building the Gate-all-around Transistor
Building the Gate-all-around Transistor + 20% transistor density + 30% + 20% performance manufacturing + 30% energy efficiency steps FinFET GAA Source: Jaehun Jeong, Samsung, 2023 VLSI FET: field effect transistor; GAA: gate-all-around Applied offers more than 10 technologies to build gate-all-aroun
Slide 44: Gate-All-Around and Beyond
Gate-All-Around and Beyond N P N P GAA GAA with GAA with Isolation CFET Backside Power GAA: gate-all-around CFET: complementary field effect transistor 44 | Applied Materials External
Slide 45: Shrinking Interconnects Degrade Power and Speed
Shrinking Interconnects Degrade Power and Speed 0.25 18 Resistance and Capacitance 16 0.2 14 (arbitrary units) Higher Resistance ➔ Lower Speed 12 0.15 10 8 0.1 6 Higher Capacitance 0.05 4 ➔ Higher Power Consumption 2 smaller nodes 0 0 Interconnect Feature Size Note: General R and C Trends 45 | Appli
Slide 46: Applied's Leadership in Interconnect Manufacturing
Applied’s Leadership in Interconnect Manufacturing Dielectric (CVD) Develop and deposit specialized Copper Line materials Barrier (ALD) Prevent copper migration Via Cobalt Liner (CVD) Promote uniform copper fill Copper Reflow (PVD) Void-free line and via fill Line Planarization (CMP) Source: TechIns
Slide 47: Wiring Innovations for the AI Era
Wiring Innovations for the AI Era Press Release 47 | Applied Materials External
Slide 48: Newest Black Diamond Low-k Dielectric Film
Newest Black Diamond™ Low-k Dielectric Film Enabling interconnect scaling for 2nm and beyond ✓ Lower capacitance for faster signals and lower power ✓ Increased mechanical strength for 3D die stacking Newest Black Diamond™ ✓ Designed for all frontside and backside wiring PTOR at multiple leading-edge
Slide 49: Introducing Endura Copper Barrier Seed IMS with Volta Ru CVD
Introducing Endura™ Copper Barrier Seed IMS™ with Volta™ Ru CVD Enabling interconnect scaling for 2nm and beyond ✓ Binary system of ruthenium and cobalt enables void-free copper reflow to maximize reliability and increase yield ✓ Thin binary liner maximizes copper volume ✓ 25% lower electrical resis
Slide 50: Integrated Materials Solution for 2nm Node and Beyond
Integrated Materials Solution for 2nm Node and Beyond CVD Endura™ CuBS IMS™ with Volta™ Ru CVD CVD CVD 1. Surface Preparation PVD Reflow PVD Reflow 2. Barrier Deposition 3. Material Modification ALD ALD 4. Ruthenium Deposition 5. Cobalt Deposition Treatment PVD 6. Copper Reflow ALD: atomic layer dep
Slide 51: Backside Power Delivery
Backside Power Delivery Frontside power in power signal signal lines lines Over 10 metal layers Large voltage drop power rail power transistor Si power µ-TSV lines Area consumed for power delivery Power lines power delivery Transistor moved to back of wafer Increases area scaling by up to 30%1 Power
Slide 52: Multiple Approaches with Scaling vs. Complexity Trade-offs
Multiple Approaches with Scaling vs. Complexity Trade-offs Buried Power Rail Power Via Direct Backside Contact power buried n-TSV via backside power rail contact power delivery power delivery power delivery Area Scaling Good Better Best Process Complexity Low Medium High Source: Adapted from Song et
Slide 53: Simplified Direct Backside Contact Process Flow
Simplified Direct Backside Contact (DBC) Process Flow frontside transistor backside Carrier Wafer DBC bonding isolation flip bonding bonding Device Wafer Device Wafer Carrier Wafer Carrier Wafer ▪ transistors ▪ fusion bond to ▪ flip wafer ▪ backside isolation ▪ contact / MOL carrier wafer ▪ extreme
Slide 54: DBC Technology Challenges: Low-temperature Backside Contact
DBC Technology Challenges: Low-temperature Backside Contact Direct Backside Contact (DBC) Low-temperature Selective Epitaxy Low-temperature Metallization Module Selective Mo gapfill with low R Low- temperature Selective Epi Selective MoSi metallization for low interface for PMOS resistance Low inter
Slide 55: Applied's Logic Innovations Enable Energy-Efficient AI
Applied’s Logic Innovations Enable Energy-Efficient AI BLACK DIAMOND™ AND GATE-ALL-AROUND BACKSIDE POWER DELIVERY CuBS IMS™ WITH VOLTA™ Ru CVD Increases logic density up to 20% Increases area scaling up to 30%1 Binary liner lowers line resistance vs. FinFET up to 25%3 Decreases power consumption up
Slide 56: DRAM
DRAM Sony Varghese, Ph.D. Senior Director of Technical Marketing, Semiconductor Products Group JULY 9, 2024
Slide 57: AI Requires Advances in Memory
AI Requires Advances in Memory AI Training Workloads Accelerating Processor-Memory Performance Gap 1e+4 AlphaGo Zero 100,000 1e+2 Neural Machine Translation TI7 Dota 1v1 1e+0 10,000 ResNets Petaflops/s-days VGG 1e-2 Performance 1,000 1e-4 AlexNet Processor 1e-6 “Memory Wall” Deep Belief Nets and 100
Slide 58: DRAM Roadmap
DRAM Roadmap 8F2 6F2 4F2 RCAT BCAT VT 3D DRAM bitline wordline 2F 4F 2F 3F 2F storage node bit line contact 2F contact RCAT: recessed channel array transistor BCAT: buried channel array transistor VT: vertical transistor 58 | Applied Materials External
Slide 59: DRAM Scaling Levers
DRAM Scaling Levers 6F2 BCAT Scaling Key modules Current Inflections lever capacitor thinner shrinking active area capacitors active area Capacitor Cell Active silicon area Word line / bit line Poly Metal Gate SiON High-k Interconnect Periphery Si Si Transistor Cu Black DiamondTM Low-k dielectric fi
Slide 60: DRAM Roadmap
DRAM Roadmap 6F2 4F2 drain drain source vertical channel U-shaped channel source DRAM Array DRAM Array Sense Amp / Decoder area savings Buried channel transistor Vertical transistor DTCO: Vertical transistor DRAM with wafer bonding can increase bit density by 30% 60 | Applied Materials External
Slide 61: DRAM Roadmap
DRAM Roadmap 8F2 6F2 4F2 RCAT BCAT VT 3D DRAM bitline wordline 2F 4F 2F 3F 2F storage node bit line contact 2F contact RCAT: recessed channel array transistor BCAT: buried channel array transistor VT: vertical transistor 61 | Applied Materials External
Slide 62: 3D DRAM Will Be Different from 3D NAND
3D DRAM Will Be Different from 3D NAND 3D DRAM must operate 1,000X faster than NAND NAND cell DRAM cell Purpose Storage memory Working memory Write speed 50,000 ns 10 ns Endurance 1e4 cycles 1e18 cycles Channel mobility Low (poly Si) High (Si) Storage discharge Slow (charge trap) Quick (capacitor) 3
Slide 63: Applied's Materials Engineering Capabilities for 3D DRAM
Applied’s Materials Engineering Capabilities for 3D DRAM 1 >100 Layer 2 High Aspect 3 Lateral 4 Form Lateral Mold Stack Ratio Etch Recess Junction Si + SiGe epitaxy >100:1 aspect ratio >100:1 selectivity Selective deposition 1 2 3 4 Images source: Applied Materials 63 | Applied Materials External
Slide 64: High-Bandwidth Memory
High-Bandwidth Memory Jinho An, Ph.D. Account Technologist Director, Semiconductor Products Group JULY 9, 2024
Slide 65: High-Bandwidth Memory
High-Bandwidth Memory DRAM chip DRAM HBM HBM stud & DRAM micro- bump HBM HBM COMPUTE ACCELERATOR DRAM HBM HBM TSV controller HBM HBM die AI Accelerator Stacking Elements logic controller die HBM Stack 65 | Applied Materials External
Slide 66: HBM: Incremental Materials Engineering Steps
High-Bandwidth Memory: Incremental Materials Engineering Steps TSV Etch CVD Liner PVD Barrier-Seed Cu Plating CMP DRAM Wafer TSV Formation Frontside Steps common for standard and HBM Bump Bond Pad Formation PVD Cu Plating Resist Strip Under-Bump Etch DRAM nodes, e.g. 1A, 1B, 1C. (frontside) >700 ste
Slide 67: High-Bandwidth Memory Controller Die
High-Bandwidth Memory Controller Die HBM3E HBM4 Planar FinFET Data Transfer Speed Transistor Density Power Consumption logic controller die 67 | Applied Materials External
Slide 68: Hybrid Bonding for High-Density Chip-to-Chip Interconnects
Hybrid Bonding for High-Density Chip-to-Chip Interconnects Microbumps ▪ 80% lower thermal resistance than microbumps TSV ▪ Enables 10,000 to ~1M connections per mm2 ▪ Demands extreme process and alignment precision microbump TSV Hybrid Bonding Integrated tool for hybrid bonding in development Source
Slide 69: Heterogeneous Integration
Heterogeneous Integration Sarah Wozny, Ph.D. Director, Semiconductor Products Group JULY 9, 2024
Slide 70: AI Accelerates Transition to Advanced Packaging
AI Accelerates Transition to Advanced Packaging AI Training Workloads Accelerating Server Die Sizes Increasing Beyond Reticle Limit 1e+4 1800 AlphaGo Zero B100 1e+2 Neural Machine 1600 Translation TI7 Dota 1v1 1e+0 AMD (GPU) 1400 ResNets Die Size (sq mm) Petaflops/s-days VGG 1e-2 1200 AMD (CPU) 1e-4
Slide 71: Advanced Packaging Roadmap Drivers
Advanced Packaging Roadmap Drivers Die stacking Interconnect scaling Panels 71 | Applied Materials External
Slide 72: Localizing Memory Reduces Power Consumption
Localizing Memory Reduces Power Consumption GDDR5 Hybrid-Bonded HBM SRAM GPU SRAM GPU GPU SRAM Energy to Fetch a Bit ~12pJ/bit <4pJ/bit <1pJ/bit from Memory: S. Naffziger, AMD, IEDM 2023 72 | Applied Materials External
Slide 73: Packaging System Interconnect Scaling Roadmap
Packaging System Interconnect Scaling Roadmap Hybrid Bonding (chiplet stacking) Through-Silicon Vias (chip stacking) I/O density (finer pitch) Microbumps 10,000 to ~1M I/O / mm2 (chip stacking) Power: <0.05 pJ / bit Bump to PCB < 10,000 I/O / mm2 > 0.1 pJ / bit Wire Bond < 1,000 I/O / mm2 > 0.5 pJ /
Slide 74: Panel Processing Enables Larger Packages for AI
Panel Processing Enables Larger Packages for AI ▪ Round wafers have poor area efficiency ▪ Panels enable packages as large as 10,000mm2 Silicon wafer Panel 300mm diameter 510x515mm Source: Applied Materials 74 | Applied Materials External
Slide 75: Glass Enables Larger and Faster Packages for AI
Glass Enables Larger and Faster Packages for AI AI Package Material Glass Organic GPU HBM Requirements Properties Mechanical 6X 1X stiffness Larger Packages interposer Thermal expansion 0.1X 1X substrate Faster Signal Loss tangent 4X 1X Propagation PCB Source: Adapted from Yole Intelligence, Status
Slide 76: Applied is Accelerating the Panel Ecosystem
Applied is Accelerating the Panel Ecosystem Lithography Deposition Test Absolics™ Joint Venture Applied leveraging its front-end process technologies and display expertise for panel packaging Maskless digital lithography Topaz™ for panels up to eBeam test technology Glass panel manufacturing for sub
Slide 77: High-Performance Photonics Platform at Scale
High-Performance Photonics Platform at Scale Press Release Modeling and Advanced Process Metrology and Scale-Up and Design Materials Capabilities Inspection Automation Glasses Prototyping Applied’s Photonics Materials-to-Systems Platform 77 | Applied Materials External
Slide 78: AI Design Forum 2018
AI Design Forum™ 2018 Tuesday, July 10, Yerba Buena Theater, SF Gary Dickerson CEO Applied Materials 78 | Applied Materials External
Slide 79: Enabled by New Architectures, Structures and Materials
ENABLED BY New architectures New structures / 3D New materials New ways to shrink Heterogeneous integration 79 | Applied Materials External
Slide 80: Growing Our Opportunity and Share
Growing Our Opportunity and Share Prabu Raja, Ph.D. President, Semiconductor Products Group JULY 9, 2024
Slide 81: The Race for AI Leadership – Fueled by Materials Engineering
The Race for AI Leadership – Fueled by Materials Engineering 81 | Applied Materials External
Slide 82: Materials Engineering Has Been ~50% or More of WFE
Materials Engineering Has Been ~50% or More of WFE WFE Mix Trend 100% Other Litho/ 2012–2017 track/ 75% mask 2D to 3D NAND conversion Process control 50% Cleans 2018–2023 EUV in leading-edge F/L and DRAM increased litho 25% Materials spending and reduced Engineering multipatterning steps 0% 2011 201
Slide 83: Applied Has Gained Share in Materials Engineering and WFE
Applied Has Gained Share in Materials Engineering and WFE WFE Mix Trend Applied Materials Positions 100% Other Litho/ track/ 41% mask 75% 35% 35% 35% Process 34% control 31% 50% Cleans Materials Engineering 21.2% 21.6% 20.5% 20.6% 19.3% 19.9% 25% Materials Engineering WFE 0% 2011 2012 2013 2014 2015
Slide 84: Materials Engineering-Enabled Technology Inflections
Materials Engineering-Enabled Technology Inflections PVD High-Performance Logic Compute Memory Advanced Packaging 6F2 VT 4F2 Gate-All-Around1 Planar DRAM Scaling3 High-Bandwidth Memory5 Density +20%, energy efficiency +30% Density +30%, energy efficiency +15% Density +250%, bandwidth +1,000% Backsid
Slide 85: Expect Materials Engineering to Increase within WFE Mix
Expect Materials Engineering to Increase within WFE Mix Materials Engineering vs. Litho/Track WFE Mix* LOGIC DRAM 100% Litho/Track Materials Engineering 0% 20nm+ 16/14nm 7nm 5/4nm 3nm GAA+BPD D1a D1b D1c D1d VT 4F2 3D DRAM Materials engr % of incremental WFE* >50% >40% >40% >60% >75% >60% >70% >40%
Slide 86: Materials Engineering Inflections Increase Applied's Opportunity
Materials Engineering Inflections Increase Applied’s Opportunity Applied’s 2023 Market Share Expect Inflections to be Accretive to SAM and SAM Share Total WFE share 21.6% TRANSISTOR + WIRING = TOTAL SAM Frontside FinFET, no GAA + Leading-edge F/L ~21% FinFET GAA Frontside SHARE BY DEVICE + Backside
Slide 87: Advanced Logic Growth Opportunities
Advanced Logic Growth Opportunities ~$7B Logic Transistor ~$6B ▪ Unique connected portfolio of materials SAM* engineering technologies ▪ Incremental steps add ~$2B SAM to Applied’s leadership segments FinFET GAA Expected SAM Share: <50% >50% GAA BPD » ALD » Implant » ALD » CMP » Process Control » CM
Slide 88: DRAM Growth Opportunities
DRAM Growth Opportunities DRAM Vertical Transistor (4F2) SAM* ~$7.5B ▪ Materials engineering steps increase ~$6.5B ▪ Uses Applied’s leadership transistor and ~$6.0B packaging technologies ▪ Bonding of DRAM cell and periphery CMOS wafers increases Applied’s opportunity 3D DRAM ▪ Further increase in m
Slide 89: Packaging Growth Opportunities
Packaging Growth Opportunities High-Bandwidth ~$0.6B Memory SAM* ~$0.45B Industry’s broadest and most connected heterogeneous integration portfolio: High-Bandwidth Memory No HBM TSV + µbump TSV + HB » Serve 14 of 19 ME steps in TSV + µbump Expected SAM Share: <50% >50% » Hybrid bonding increases SAM
Slide 90: Applied's AI-Fueled Growth Thesis
Applied’s AI-Fueled Growth Thesis 1. Semiconductors Global GDP significantly outgrow GDP 2. Fab equipment grows as fast Semiconductors or faster than semiconductors 3. Applied Semi Systems outgrows fab equipment market Wafer Fab Equipment 4. Applied Global Services grows as fast or faster than Appli
Slide 91: 2024 SEMICON West Technology Breakfast
2024 SEMICON WEST TECHNOLOGY BREAKFAST
Applied Materials — 2024 SEMICON West Technology Breakfast on 6ix