Asml Holding Nv · EURONEXT:ASML
Asml Holding Nv — Investor Day (November 2014)
53 slides from Asml Holding Nv's investor day presentation, Nov 24, 2014
Slide 1: Many ways to shrink: 10 nanometer and beyond
EX-99.3 4 d826396dex993.htm EX-99.3 Exhibit 99.3 Many ASML The Martin President 24 INVESTOR LONDON ASMLSMALLTALK2014 November right ways vanmoves &den to Chief DAY 2014 shrink: Brink toTechnology 10 nanometer Officer and beyond
Slide 2: Forward-looking statements
Forward Slide Public ASML November This segments, margin expected shipments, of new Law, “plan”, assumptions Forward-looking equipment confidence performance roadmaps, ability litigation, available underlying acquired are our made applications document and 2tools, to percentage, “estimate”, looking
Slide 3: Content: shrink challenges and solutions
Slideprocess Public November Industry Content ASML Our The desire device scaling holistic 3 Solutions Challenges to 2014 challenges challenges approach simplification shrink to extend by using immersion EUV
Slide 4: Moore's Law: benefits of shrink are irresistible
Moore’s The Slide Public ASML November benefits 4 Law: 2014 ofthe shrink rice-and-chessboard are irresistible challenge
Slide 5: Moore's 1965 prediction
Driving “...home Slide Public ASML November Gordon Integrated electronic But telephone Reality, Source: “Cramming Electronics, the 5 biggest Gordon Moore’s ~ the computers... 50 circuits wristwatch circuits 2014 semiconductor More pp114-117, years potential E. prediction, and Components will Moore,
Slide 6: Some discussions about the end of Moore's Law
Some Slide Public ASML November C|net End about A by Hot ZDNet White Newsletters Downloads Reviews Work, PCWorld Seeking Read. Intel: OK, end Moore’s Semiconductor Moore discussions Cost 16/14nm .0162 20nm .0142 28nm .0140 40nm .0194 65nm .0282 90nm .0401 .0000 .0050 .0100 .0150 .0200 .0250 .0300 .0
Slide 7: Mobile applications continue to drive shrink
Mobile Slide Public ASML November 28HKMG 28PolySiON 20HKMG Transistor 14/16FF Litho ‘12 Source: ‘13 710FF applications ‘14 Esin Area Power Performance 2014 ‘15 Terzioglu, ‘16 continue Qualcomm, to be on EUV an yearly symposium, cadence Oct device 2014and litho innovations driving area, power and per
Slide 8: Mobile Apple: shrink and added functionality
Mobile Apple: Slide Public ASML November Add New De-featuring Apple IC Source: 20nm 28nm 32nm 45nm Shrink Functionality Dual 8A7 A6x A4 A5 A5X A5S A5_3 first chips Apple 1-Core -2-Core 41% 15% 12% Core 2014 –iPhone high --Apple iPad integrating Apple and and volume and 35S added TV, 2-Core 4-GPU TV1
Slide 9: Capital growth and cost per transistor
And Slide Public ASML $/mm2 100 m $X = 10Normalized 0.13 0.01 90 65 45 32 22 14 710 Source: .13 /transistor .1 nm* m2/transistor nm nm* area um 9 November Bill andArea/Transistor Capital Cost Holt, costper Intel, per 2014 Growth Transistor function “Intel Growth ($/mm2) Investor reduction ($/transis
Slide 10: Scaling is a competitive item between chip makers
And Scale Slide Public ASML November Area Log Intel’s Intel ~45% *35% ~15% TSMC 32/28 1Bill Sourcews: 2Mark isScaling Holt, 10 nm view aLiu, reaction competitive 22/20 2014 Intel TSMC on TSMC’s on nm investor Intel2 analyst 14 item nm*/16FF shrink1 conference, between call, Jan10 chip 2014 Nov nm*ma
Slide 11: The challenge of Moore's law in numbers
The What Slide Public ASML 1November 256 65536 16777216 4.29E+09 1.1E+12 2.81E+14 7.21E+16 2 4512 challenge 811 about 131072 16 1024 2.2E+12 8.59E+09 5.63E+14 1.44E+17 32 33554432 2014 our 64 2048 of 262144 customers 128 Moore’s 4.4E+12 4096 1.72E+10 1.13E+15 2.88E+17 67108864 524288 8192 law challe
Slide 12: Shrink scenarios for logic devices
Shrink Slide Public ASML November SOURCE Complementary SOI: N10 Bulk fin SOI silicon N Gate-all-around 5720 field /FinFet Partially Fully CMOS CMOS: FinFet /N 12 N on scenarios 5effect 3.5 14 7insulator GATE 2014 depleted : :atdepleted transistor 100 transistor Metal for DRAIN fin nm Silicon logic O
Slide 13: Shrink scenarios for logic devices at 20 nm
Shrink Slide Public ASML November SOURCE Complementary SOI: N10 Bulk fin SOI silicon N Gate-all-around 5720 field /FinFet Partially Fully CMOS CMOS: FinFet /N 13 N on scenarios 5effect 3.5 14 7insulator GATE 2014 depleted : :20 depleted transistor nm: transistor Metal for DRAIN fin Silicon logic ope
Slide 14: Shrink Solution 1: Silicon on insulator
Shrink Slide Public ASML November Solution Silicon SOURCE Complementary SOI: N10 Bulk fin SOI silicon N Gate-all-around 5720 field /FinFet Partially Fully CMOS: FinFet /N 14 N on scenarios on 5effect 3.5 1: 14 7insulator GATE insolator 2014 depleted : : depleted transistor transistor Metal for DRAIN
Slide 15: Shrink Solution 2: FinFET
Shrink Slide Public ASML November Solution SOURCE Complementary SOI: N10 Bulk fin SOI silicon N Gate-all-around 5720 field /FinFet Partially Fully CMOS: FinFet /N 15 N on scenarios 5effect 3.5 2: 14 7insulator GATE 2014 depleted : : depleted transistor transistor Metal for DRAIN fin Silicon logic Ox
Slide 16: Shrink: Gate all around
Shrink Slide Public ASML November Gate SOURCE Complementary SOI: N10 Bulk fin SOI silicon N Gate-all-around 5720 field /FinFet all Partially Fully CMOS: FinFet /N 16 N on scenarios 5around: 3.5 effect 14 7insulator GATE 2014 depleted : : depleted transistor transistor Open Closed Metal for DRAIN fin
Slide 17: No end in sight for scaling
No5720 Slide Public ASML November Complementary SOI: N10 Bulk fin SOI silicon N Gate-all-around field end /FinFet Partially Fully CMOS: FinFet /N 17 N on in 5effect 3.5 14 7insulator sight 2014 depleted : : depleted transistor for transistor Metal logic fin Silicon Oxide field Silicon scaling on eff
Slide 18: Significant memory innovations ahead
Significant Slide Public ASML November Speed Working Storage DRAM SRAM Cost NAND On-chip ReRAM/STT-MRAM Endurance 3D-ReRAM PCRAM/ReRAM Source: Capacity Retention 18 &HDD Class Meng-Fan NVM Bandwidth Memory 2014 architectural 3D-NAND Memory Chang, eFlash innovations NTU Taiwan, ahead Resistive for Me
Slide 19: 3D NAND patterning challenges
Slide Public ASML November Cell 20nm 110nm Over Design e- 2D 83D 16Gb ‘03 128Gb Source: 2e-Aspect stack V-NAND NAND Cell Planar ‘05 Cell 30nm 19 128Gb 24 Rule ‘07 Jung, to stack cell ratio 2014 vs ‘09 D/R (nm) 1Tb /Samsung, 3D No interference ‘11 Over V-NAND Patterning ‘1330nm ‘15 Flash ‘17 Challeng
Slide 20: 3D NAND and ReRAM extensions
Slide Public ASML November 2D Scalable Cost NAND 3D 2013 RAM 19 BiCS ReRAM Source: nm extensions, NAND ReRAM Resistive 2014 20 Bit Pilot, 15 memory Siva Technology 3D nm2014 2015 3D Sivaram, …?3D Productions continuing 2016 X2, introduction Development x3 2017 Sandisk X2,onx3multiple investor and Re
Slide 21: 3D NAND scaling potential and new product categories
Slide Public ASML November 2D BiCS Cost NAND Scalable RAM Lower Scaling Higher 3D Source: extensions, NAND Resistive Stacking ReRAM 21 Bit Latency Power/Energy Endurance memory Potential Siva 3D2014 BelowSivaram, 3D 10 continuing introduction nm;Sandisk NewonProduct multiple investor and ReRam Categ
Slide 22: New memory timelines
Slide Public ASML November 2D BiCS Scalable Cost Memory RAM 2013 DRAM NAND 3D New 50 Top Cu Dielectric Electrolyte Bridge Hybrid Resistive Source: Scott nm Ion extensions, NAND ReRAM Resistive Packaging Electrode Memory 2014 22 DeBoer, Bit Reservoir Memory memory 16nm 25nm Siva 3D Technology RAM BE
Slide 23: Critical etch and litho requirements for 3D memory
Critical Etch Slide Public ASML November Vertical Gates Large Cross Perpendicular Lithography Deposition Scalable aspect 23 around bar gate requirements NAND gate ReRAM 2014 size and ratio light, intensive possible conductive gate deep litho vscritical and litho etch for (< channel scaling vertical
Slide 24: DRAM and its cost reduction
and its Slide Public ASML November Cost PCRAM ReRAM STT-MRAM DRAM Intercept NAND New Time Source: Reduction memory Memory 24 &likely 3D NAND Managed S.W. Tech .. 25nm 42nm 2014 NAND delayed Park, Node competes Slow Rate Tech 1Gb DRAM Hynix, Tech .transition 25nm with Maturity ITPC DRAM 16Gb determin
Slide 25: Sub-resolution multiple patterning
Sub-resolution Slide Public ASML November Process 2D LELE LELELE LE 1D SADP SAQP Mandrel Spacer Patterning Overlay Suitable May #1 Multi Self need 25 (or LE (D=Double) (Q=Quadruple) #1 #2 cut Aligned Flow control for (or Patterning EUV #2 multiple cut(s) 2014 1D EUV LEimaging SE) or layout of Multip
Slide 26: 10nm 1D vs 2D design
10nm ..but 2D Die 1D Slide Public ASML November size: at26 logic the115% 100% 2014 penalty design can of 15% be done largerindie 1Dat comparable design rules
Slide 27: EUV: allowing design simplification
EUV: Allowing Slide Public ASML November Able Better Reduced TOP TIN 193i EUV Cross-section PO FIN MP MD V0 M1 See Source: next view to 27 reduced freedom employ Esin slide MOL 2D 2014 Terzioglu, structures showing complexity complexity for jogsredundant Reduced connections Qualcomm, and& by potenti
Slide 28: 10nm patterning cost options
10nm Slide Public ASML November EUV Good Insufficient NO ArFi Cost 1-2 extra SOLUTION for LE4 –lowest 2D 28 pattern patterning 1D 1structure 2-3 layers 2D layer only 2014 pattern layers cost fidelity structure 6-8 needed 100% ~choices and 170% Single >fidelity exposures 250% Re-use complexity Single
Slide 29: Continued cost reduction needs innovation
Continued but Slide Public ASML November Relative 65 Technology “traditional -??? Source: Primary New Multi-pattern EUV Design/tech ….45 significant 29 28 Materials lithography Esin Cost 20/14 culprit: significant 2014 path” Node Terzioglu, co-optimization Per innovation cost 107 Opportunities litho
Slide 30: EUV N7 vs 193i
EUVN7-193i Slide Public ASML November Doubling “Relative N10 Source: supports 30Esin Cost” functionality 2014 Terzioglu, N7-EUV “free functionality” (2x LS Qualcomm, # gates)for node-to-node EUV the symposium, 7nm node Oct 2014
Slide 31: Industry roadmap summary
Industry Slide Public ASML November NAND DRAM LOGIC MPU 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 Single Double Note: *EUV Q2-2013 22 35 28 19 17 15 16 12 25 10 11 8RERAM8lyrs 31 Node expose /patterning /Node STT-MRAM 38 52 48 33 28 43 3D32lyrs RERAM8lyrs production Non V
Slide 32: Industry roadmap summary with EUV insertion
Industry Slide Public ASML November NAND DRAM LOGIC MPU 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 Single Double Note: *EUV Estimated Q2-2013 22 35 28 19 17 16lyrs 24lyrs 32lyrs 16 12 25 10 11 8RERAM8lyrs 32 Node expose /patterning /Node STT-MRAM 38 52 48 (1270) 14 3D32lyr
Slide 33: During the past years our customers moved to shrink
Our During Slide Public ASML 6November Jack High-end 128 256 12 65536 16777216 4.29E+09 1.1E+12 2.8 7.21E+16 Gb4.5 Gb 512 customers Kilby’s DRAM: 33 131072 the SLC 1024 12 MPU: GPU: FPGA: 8.59E+09 1.44E+17 33554432 2014 past 4.4E+12 first NAND: 16384 626214 moved 66 billion 75120 billion billion yea
Slide 34: Customer roadmap summary
Customer Slide Public ASML November Significant Logics Memory Continued EUV to 34environment bring roadmap roadmap shrink 2014 innovation process planned tosummary very besimplicity ahead diversified competitive forin thelogic allowing next through including relative 10 years 2D thelayout tooffering
Slide 35: Content: holistic approach
Slideprocess Public November Industry Content ASML Our The desire device scaling holistic 35Solutions Challenges to 2014 challenges challenges approach simplification shrink to extend by using immersion EUV
Slide 36: Multi-patterning complexity explodes using immersion
Slide Public ASML November Multi-patterning 5A 4A 3A Layers 1A 0A Masks #Node of0A OVL 5A 4A overlay 1A lithography 36 28nm 5A 4A 1A 0B Masks 21A metrology 5B 4B 1B 0A 2014 measurements Layers 21B 20nm 5C 4C 1C 0B Masks steps 21C complexity 5A 4A 1D 0C 710nm 21A 9-11 0D 5B 4B 1A Masks 21D 6 821B 5C
Slide 37: Our challenge: affordable scaling
SlideChallenge: Public ASML November Our Scaling Affordable Holistic Immersion: EUV: 37 drive needs Lithography 2014 scaling productivity drive tokeep create productivity in scaling with lithography lower and both affordable improve cost and EUVcan and yield and be operational improved (overlay achi
Slide 38: Holistic lithography: linking six elements
Slide Public November ASML Linking 4. 1. 5. Stepper Design Product 3. 6. 2. Advanced BRION Process Metrology 38holistic context set control reticles wafers thewindow Computational 2014 up scanner lithography and and lithography used through control layout enlargement control detection to to YieldSta
Slide 39: 1) Enabling immersion extension
Slide Public ASML November 1) Enabling Application Logic 28 2M 20/16/14 SNEP 10 7SNEP: 1M TWINSCAN 2H 1H NXT:1960Bi 39 PEP: DRAM 1NXT:1980Di 2NXT:1950i System NXT:1965Ci 2L extension 2014 Productivity Node NXT:1970Ci 190 Node immersion 6.5 On 7WpH of <3.5 nm Extension nm product PEP customer 2009 En
Slide 40: 2) Providing YieldStar metrology
Slide Public ASML November 2) Providing Illumination •Sensor: MA 1$S-250D $200 1.2 0L 0.2 0.4 0.6 0.8 TMU Average 200-X Layers 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 250 Wavelength Laser Narrow Optics Faster ayers YieldStar time(s) 40 [nm] 200-Y Pumped cameras to ofand Overlay, 2014
Slide 41: 3) Litho model calibration
Slide Public ASML November 3) 10nm Model M1 Litho Logic Source: SRAM Negative 41 1node 2 3standard calibration Imec 2014 metal tonecell develop layer RMS:wafer 2nm model results (1Dvalidation & (triple 2D), Wafer patterning, DOF: LELELE) 80nm, Across wafer CDU: 1.1nm
Slide 42: 4) Exposure source optimization
Slide Public ASML November 4) Exposure Anchor Logic SRAMs 10 Tachyon Standard +23% DoF 02= Depth 100 80 60 40 10nm One Source: 070 86 Source-mask 8 common 6@ nm 42 node of 45% Imec 2SMO Focus annular Latitude 02014 metal1: ELsource (nm) optimization (%) 48nm optimized min.ofpitch, for flexible best
Slide 43: 5) Integrated metrology overlay
Slide Public ASML November 5) Max Standalone 10 5Integrated 20% OPO 1Lots One Each Litho-clusters 21 20% scanners, month 41 run improvement Overlay data spec 43improvement 61 onpoint metrology 2014 81 metrology production YieldStar 3per 101 YieldStar is with Lot one 121 with YieldStar (IM) _X in (S
Slide 44: 6) Overlay measurement accuracy
Slide Public ASML November •6) 16 R2 00.7 Total Physical Floor DSWA Asymi OVL MIN Overlay Physical 2Computational 14 =4 0.7 Marker, 0.8719 0.3914 6Measurement 44 Tilt 12 =8 0.6 simulated accuracy (Accuracy) KPI overlay, overlay {DSWA, 10 overlay 2014 0.6 8(marker, 12recipe 60.5 14 4measurement (meas
Slide 45: Printing history on the chessboard
Slide Public November ASML 31973: 5.4 1984: 1,2 61 2014: 19 114 256 65536 16777216 4.29E+09 1.1E+12 2.81E+14 1.44E+17 Contact 1:1 DUV 2um, Tpixel/s Mpixel/s nm, Mpixel/s um, 4 scanners 512 845 step 75 1:1 G/H 193 131072 enabled 16 300 100 printing 1024 2.2E+12 mm Scanners, 8.59E+09 5.63E+14 2.88E+17
Slide 46: EUV simplifies multi-patterning
Slide Public ASML November Multi-patterning 4A 3A 21A 1A 0A 5A 10nm 20nm 28nm Node EUV Layers Masks #7nm of4A OVL 5B 4B 3B 1B 0B lithography 21B all 463A 5C 4C 3C 1C 0C metrology immersion EUV 22A 3B 3D 1D 0D 21A 2014 21A 0E 22B 1A 22A steps could 70A 1A 1A 9-11 60A explode, 1B 836-40 0B 23 0A340B 5
Slide 47: NXE:3300B imaging and overlay
Slide Public ASML November NXE:3300B Good NXE:3300B, 60nm 0nm -60nm Focus Full realized, 85% transmission an Matched 5progress EUV 1Overlay Source: 24.5 evaluation 3size (single 4to 47 imaging, 3.5 ST, Immersion Y X103x122 pSi Machine 2014 32014 pass) litho 2.5 pellicle mounting 10 inoverlay 2nm per
Slide 48: NXE:33x0B productivity
Slide Public ASML November NXE:33x0B Up Exposed 100 Proto NXE:3100 Expose Projected Demonstrated NXE:3300B (@customer Lot 40W NXE:3350B 1200 Equivalent 2Q12 oTime Dose-to-expose Productivity: NXE:3350B to overhead 90 80W 1000 48 2Q13 780 speed systems speed WPD 70 100W 2014 800 Productivity 4Q13 con
Slide 49: High-NA EUV on roadmap
Multi-patterning >0.5 Slide Public ASML November 5A 5B Layers 7nm Node Masks 5nm #93nm 12of18-22 12 OVL 5C 4A 5A lithography 19 -high-NA 49 EUV high 5A 3A 4B metrology 9 29-36 12 22A 4A 4B 2014 NA4C 3A will 21A EUV 12 steps planned 4A 3Bsimplify 18-22 1A 22A 3A1B 3B with 21A 0A and 3CEUV 0B 1A3D ext
Slide 50: We are preparing the next move 2019/2024
We Our Slide Public ASML November 32019-2024: 1200 256 65536 16777216 4.29E+09 1.1E+12 2.81E+ 7.21E+16 Contact 2019/2024 2014 1984 1973 19581 1:1 DUV 1Jack EUV 2nm, 4scanners are W/hr, 512 next 850 step Kilby’s 300 131072 16 preparing 1.13E+15 printing 1024 2.2E+12 move: 8.59E+09 1.44E+17 0.45 128 3
Slide 51: Summary
Slide Public Summary November Node To ASML EUV Lithography address infrastructure 51 progression has 2014 highly demonstrated roadmap enabled complex supportive defined consistent by multi-patterning immersion down for above EUV to thetransition multi source 3nm schemes, pass node progress. scenario
Slide 52: Moore's chessboard story
Hadcould Slide Public ASML November He would the 52 King’s have have 2014fed worked name thebeen world, to find Moore…. instead ways to ofscale having down lost his a Kingdom. grains, keep their nutritional value and double the amount with every move.
Slide 53: Investor Day ASML London
INVESTOR DAY ASML LONDON ASMLSMALLTALK2014