Slide 1: EUVL – getting ready for volume introduction
EUVL – getting ready for volume introduction SEMICON West 2010 Hans Meiling, July 14, Slide 2010 1 | public
Slide 2: Outline
Outline • ASML’s Lithography roadmap to support Moore’s Law • Progress on 0.25NA EUV systems • Progress on 0.32NA EUV systems • Outlook Slide 2 | public
Slide 3: Outline
Outline • ASML’s Lithography roadmap to support Moore’s Law • Progress on 0.25NA EUV systems • Progress on 0.32NA EUV systems • Outlook Slide 3 | public
Slide 4: IC & Lithography roadmap towards <10nm
IC & Lithography roadmap towards <10nm 200 Resolution (half pitch) "Shrink" [nm] Logic / SRAM KrF 100 80 ArFi ArF AT:1200 60 6 Transistor XT:1400 50 SRAM Cell XT:1700i k1 0.40 ~ 0.44 40 DRAM NAND Flash XT:1900i NXT:1950i DPT 30 LOGIC EUV-ADT DPT 20 NXE:3100 NXE:3300B DRAM EUV NXE:3300C DPT² 10 k1 0.
Slide 5: Litho costs back to normal with EUV >100 W/hr
Litho costs back to normal with EUV >100 W/hr 3.5 DPT case, Litho cost EUV case, Litho cost increases 2 ~ 3 times trend returns 3 Litho cost per wafer [a.u.] 2.5 2 1.5 1 0.5 1st Gen. 2st Gen. DTP DTP 0 KrF set 1400 set 1900i set 1900i DPT 1900i DPT EUV EUV 100W/hr 180W/hr Source: Samsung, Prague, oc
Slide 6: EUV can increase the fab capacity 2x
EUV can increase the fab capacity 2x Larger footprint required to support Multi Patterning schemes Track NXE NXT Etch CVD Strip Spacer double EUV patterning 1200 m2 clean room 627 m2 clean room OR 130k Wafers / Month 250k Wafers / Month Slide 6 | public
Slide 7: Critical issues EUV 2005-2009
Critical issues EUV 2005-2009 2005 / 32hp 2006 / 32hp 2007 / 22hp 2008 / 22hp 2009 / 22hp 1. Resist resolution, 1. Reliable high power 1. Reliable high power 1. Long-term source sensitivity & LER source & collector source & collector operation with 100 1. MASK met simultaneously module module W at I
Slide 8: Mask infrastructure improvements on blanks & inspection
Mask infrastructure improvements on blanks & inspection near levels needed for pilot production 350 50 nm@M7360 300 60 nm@M1350H 250 Defect counts 200 1/10 150 100 50 0 Q2’08 Q4’08 Q2’09 Q1’10 ML/QZ ML/ULE Optical inspection able to detect phase defects <3.4 nm x 45.4 nm in size² 1 Source: Hoya, Sam
Slide 9: EUV resist makes steady progress
EUV resist makes steady progress Extrapolation of 2004-2010 progress matches shrink roadmap NXE:3100 (10mJ/cm2) NA/σ=0.25/0.8 50 NXE:3300 (15mJ/cm2) NA/σ=0.32/0.9 NXE:3300 (15mJ/cm2) NA/σ=0.32/dipole 45 Node Introduction 40 22nm dense lines Resolution 35 Dose 12.8mJ/cm2 4.3nm LWR 0.3NA small field 3
Slide 10: EUVL Roadmap supports many generations of shrink
EUVL Roadmap supports many generations of shrink 2006 2010 2012 2013 Proto System NXE:3100 NXE:3300B NXE:3300C Resolution 32 nm 27 nm 22 nm 16* nm NA / σ 0.25 / 0.5 0.25 / 0.8 0.32 / 0.2-0.9 0.32 / OAI Overlay (SMO) < 7 nm < 4.5 nm < 3.5 nm < 3 nm Throughput W/hr 4 W/hr 60 W/hr 125 W/hr 150 W/hr Dos
Slide 11: Outline
Outline • ASML’s Lithography roadmap to support Moore’s Law • Progress on 0.25NA EUV systems • Progress on 0.32NA EUV systems • Outlook Slide 11 | public
Slide 12: EUV process viability confirmed by two 0.25NA Systems
EUV process viability confirmed by two 0.25NA Systems λ 13.5 nm NA 0.25 Field size 26 x 33 mm2 Magnification 4x reduction σ 0.5 • 300mm Single stage • linked to track • Single reticle load • Uses TWINSCAN technology • Sn discharge source Sou ) rce: el gium Uni vers B uven, ity o f Al e EC (L ban y(
Slide 13: Overlay performance supports device integration
Overlay performance supports device integration On-product Overlay Residuals Single Machine Overlay X = 8.0 nm, Y = 7.8 nm X = 2.2 nm, Y = 2.8 nm 300 Frequency 200 100 0 300 Frequency 200 100 0 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 Error X Error Y Source: GlobalFoundries, SPIE 2010 Slide 13 | public
Slide 14: SRAM node integration after etch process
µm2) node SRAM after etch process 22 nm (0.079µ integration SRAM cell Node Half Pitch Cell size Cell size [nm] [nm] [µm2] shrink 45 80 0.314 45 70 0.274 13% 32 62 0.186 32% 22 52 0.079 58% 16 35 0.042 47% SRAM array Source: IMEC, EUV Symposium ’09 (Prague) Slide 14 | public
Slide 15: 24nm champion resolution on 0.25NA/0.5σ
σ system 24nm champion resolution on 0.25NA/0.5σ From ~32nm half-pitch in 2007 to 24nm in 2010 2.50 no underlayer underlayer 2007 TMAH dev TMAH dev 2.00 2008 blurred NILS 1.50 2009 1.00 2010 24nm HP ~19 mJ/cm2 0.50 0.00 35 30 25 20 15 L/S HP (nm) Slide 15 | public
Slide 16: NXE:3100 integration status, July 2010
NXE:3100 integration status, July 2010 Reticle Stage and Handler Reticle Handling and Stage control Vacuum in vacuum system design verified, Reliability testing since Q4/2009 <1hour pump down Source Pilot Source operational at ASML Optics 5 Optics sets delivered, Flare improved to 4% Overlay Wafer S
Slide 17: NXE:3100 integration: systems completed
NXE:3100 integration: 3 systems completed NXE:3100 #3 System completed EUV source in installation NXE:3100 #2 System completed First wafer exposed NXE:3100 #1 Integration for Imaging System completed Integration for Overlay, S/W, TPT Slide 17 | public PUBLIC
Slide 18: More NXE:3100 systems in build-up
3 more NXE:3100 systems in build-up NXE:3100 #5 Currently used for Stage test setup NXE:3100 #6 System in buildup NXE:3100 #4 System almost complete 2 more Cabins used as work centers / test rigs. All 8 cabins can be used for NXE:3300 manufacturing Slide 18 | public PUBLIC
Slide 19: Multiple 3100 lenses manufactured and qualified
Multiple 3100 lenses manufactured and qualified Wavefront qualified by EUVL interferometer RMS(Z5-Z37) 1.40 RMS(spherical) RMS(coma) 1.20 RMS(ast) RMS(3-foil) 1.00 RMS [nm] 0.80 0.60 0.40 0.20 0.00 ADT 1 2 3 4 Multiple 3100 lenses within flare specifications ~15 8 Flare below 2.0 µm 7 Flare below 2.
Slide 20: NXE metrology verified in vacuum
NXE metrology verified in vacuum Focus and Levelling Mean standard deviation over wafer: 0.9 nm 99.7% value of standard deviations: 1.6 nm Alignment Repeated readouts (drift corrected) (S2N) Static Repro results Smash 3σ on fiducial <1nm X 0.9 Y 0.8 Multiple 0.7 0.6 wafer readout [%] 0.5 0.4 3σ = 0.
Slide 21: Reliability testing ongoing on multiple systems
Reliability testing ongoing on multiple systems Focus on wafer- and reticle exchange functionality 2500 5000 • all wafer- and reticle 2250 exchanges in vacuum 4500 2000 • data summed from 3 4000 different systems Number of Chuckswaps 1750 • all exchanges under 3500 Number of Cycles full SW control 1
Slide 22: Sources integrated with systems at ASML
Sources integrated with systems at ASML First EUV exposures made Source vessel operational and integrated with scanner system First EUV wafer exposed on integrated system CO2 laser operational and integrated with scanner system Slide 22 | public
Slide 23: On-site source performance: current and expectation
On-site source performance: current and expectation Performance as installed at ASML • Two sources shipped to ASML, 3rd one in acceptance testing. • Two power upgrades* are planned • Upgrade #1 • Increased CO2 power by increased laser gain length. • Upgrade #2 • Increased CO2-to-EUV conversion effic
Slide 24: Upgrade #2: Pre-pulse proof-of-concept being validated
Upgrade #2: Pre-pulse proof-of-concept being validated 4 With Pre-Pulse Without Pre-Pulse 3 pulse-peak CE, measured 2Q’10 CE, % 2 pulse-average CE, measured 2Q’10 1 0 0 10 20 30 40 50 60 70 80 90 100 Droplet Diameter, um ● The target size and density can be optimized by striking the droplet with a p
Slide 25: Significant source progress required for NXE 3300
Significant source progress required for NXE 3300 Roadmap commitments from multiple suppliers enable NXE productivity 300 Supplier 1 Public roadmaps enable 125 wph Supplier 2 at 15 mJ/cm2: ~2x power to go 250 Supplier 3 Expose Power [W] 200 150 100 50 0 Feb 2009 Oct 2009 Apr 2010 NXE:3100 NXE:3300 S
Slide 26: Outline
Outline • ASML’s Lithography roadmap to support Moore’s Law • Progress on 0.25NA EUV systems • Progress on 0.32NA EUV systems • Outlook Slide 26 | public
Slide 27: NXE:3300B 1st shipment: H1 2012
NXE:3300B 1st shipment: H1 2012 2nd generation of NXE platform Specifications • NA = 0.32 • Resolution 22 nm; 18/16nm with OAI • Overlay 3.5 nm • Productivity 125 wph 15 mJ/cm2 resist Slide 27 | public
Slide 28: Six-mirror lens design is extendable to 0.32 NA
Six-mirror lens design is extendable to 0.32 NA Resolution improves from 27 to 22 nm • Field size 26 mm • Chief ray at mask 6° • Design complexity/cost increases • Larger mirrors • Steeper aspheric mirrors • High angles of incidence design examples 0.25 NA 0.32 NA NXE:3100 NXE:3300 Slide 28 | public
Slide 29: Further resolution improvement with off-axis illumination
Further resolution improvement with off-axis illumination With dipole illumination resolution improves to below 16 nm Conventional 3.0 ☺ 2.5 Dipole Quasar Image contrast (NILS) Annular 2.0 Target NILS = 2 1.5 CD = k1 ⋅ λ 1.0 NA 0.5 11 nm 16 nm 22 nm 32 nm 0.0 0.25 0.35 0.45 0.55 0.65 0.75 k1 half pi
Slide 30: ASML c-lithography roadmap supports EUVL
ASML c-lithography roadmap supports EUVL Support of ASML EUV scanners through Brion products 2006 2010 2012 2013 Proto NXE:3100 NXE:3300B NXE:3300C NXE models OPC & LMC SMO LithoTuner 2009.09 release 2010.06 release 2011.06 release 2012.06 release 1. Beta release 1. Production release 1. Models: NXE
Slide 31: NXE:3300 footprint target is <50% of NXE:3100
NXE:3300 footprint target is <50% of NXE:3100 Incl. shared service area, for multiple systems in fab. Service Area Sub fab Area NXE:3300 NXE:3100 Footprint NXE:3100 NXE:3300 Exposure Unit footprint: 1 0.8 Subfab footprint (excl. prepumps, abatement) 1 0.4 Total footprint (incl. service area) 1 0.4 (
Slide 32: NXE:3300 mirrors are in production at Zeiss
NXE:3300 mirrors are in production at Zeiss Slide 32 | public
Slide 33: Construction of new EUV facilities has started
Construction of new EUV facilities has started Planned NXE production capacity increases ~3x Existing EUV offices & manufacturing, 8 cabins. New EUV offices & manufacturing,15 cabins. Slide 33 | public
Slide 34: Outline
Outline • ASML’s Lithography roadmap to support Moore’s Law • Progress on 0.25NA EUV systems • Progress on 0.32NA EUV systems • Outlook Slide 34 | public
Slide 35: EUV extendibility possible beyond 10 nm resolution
EUV extendibility possible beyond 10 nm resolution Through increase of the aperture up to 0.7 Aperture 0.25 0.32 0.5 0.7 6 mirror 6 mirror 8 mirror 6 mirror 8 mirror design Unobscured Central obscuration examples Reference: W.Kaiser et al, SPIE 2008 6924-4 Slide 35 | public
Slide 36: Extendibility of EUV down to sub nm possible
Extendibility of EUV down to sub 5 nm possible Increasing apertures up to 0.7, wavelength reduction down to 6.8 nm using 13 nm compatible optics with depth of focus as the major challenge 40 0.8 k-factor@13 nm Aperture@13 nm 35 0.7 Resolution, Depth of focus [nm] k-factor@6.8 nm 30 0.6 Aperture@6.8
Slide 37: Summary
Summary • 6 NXE:3100 systems have been ordered by customers, in all market segments, worldwide. • 1st HVM source for NXE:3100 is operational at ASML. • performance supports system integration, and needs upgrades for 60 W/hr. • NXE:3100 in final integration phase for shipment H2 2010. • first wafer e
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