Intel Corporation · NASDAQ:INTC
Intel — Investor Day (May 2019)
48 slides from Intel's investor day presentation, May 9, 2019
Slide 1: Dr. Murthy Renduchintala, Chief Engineering Officer
Exhibit 99.2 DR. MURTHY RENDUCHINTALA Chief Engineering Officer, Intel Group President, TSCGExhibit 99.2 DR. MURTHY RENDUCHINTALA Chief Engineering Officer, Intel Group President, TSCG
Slide 2: Forward-looking statements
Statements in this presentation that refer to business outlook, future plans and expectations are forward-looking statements that involve a number of risks and uncertainties. Words such as anticipates, expects, intends, goals, plans, believes, seeks, estimates, continues, may, will, “would,” should,
Slide 3: Data growth and opportunity; data-centric product leadership; product highlights
= es DATA GROWTH AND OPPORTUNITY DATA-CENTRIC PRODUCT LEADERSHIP ~ PRODUCT HIGHLIGHTS
Slide 4: Data growth and compute diversity
CAGR (17-25) PB 2 ZB 15 ZB 160 ZB 20% COMPUTE DIVERSITY PRODUCTIVITY DATA BROADCAST MEDIA Scalar, vector, spatial - AI, graphics, media, analytics NETWORK CLOUDIFICATION Compute & storage distributed across WEB / MOBILE core, access, and edge networks 35% INTELLIGENT AGENTS IOT / ANALYTICS Prolifera
Slide 5: Data-centric ~$220B and PC-centric ~$68B TAM
DATA CENTRIC: ~$220B PC CENTRIC: ~$68B High growth segments 2018-23 growth relative to aggregate TAM COMPUTE DIVERSITY 10x+ NETWORK CLOUDIFICATION INTELLIGENT AGENTS 5x 2x DATACENTER Network IOT PC AND ADJACENCIES + + Source: Intel calculated 2023 TAM and growth rates derived from analyst forecasts
Slide 6: Six concurrent pillars of innovation
pc - c e n t r i c E R A D a t a - c e n t r i c E R A CPU LEADERSHIP, WORKLOAD-OPTIMIZED PLATFORMS, TRANSISTOR SCALING EFFORTLESS CUSTOMER & DEVELOPER INNOVATION SIX CONCURRENT PILLARS OF INNOVATION ACCELERATING PRODUCT ROADMAP REFRESH 6pc - c e n t r i c E R A D a t a - c e n t r i c E R A CPU LEA
Slide 7: Workload-optimized platforms and customer innovation
SW portability, reusability and performance grows in value with compute diversity Confidentiality, integrity and resiliency become increasingly critical Increased data movement makes interconnects critical to the platform Memory bandwidth/latency/cost critical to handle data Data-centric workloads r
Slide 8: Transistor scaling vs heterogeneous integration
TRANSISTOR SCALING & MONOLITHIC INTEGRATION HETEROGENEOUS PROCESSES & INTEGRATION One process design point for all products Multiple processes optimized for individual IPs Monolithic integration Multi-chip integration with advanced packaging Product restricted by reticle Product unconstrained by ret
Slide 9: Process roadmap: 10nm scaling
Transistor efficiency (Perf / W) Most ambitious scaling in history 10 u 2.7x density scaling u Self-aligned Quad-patterning u Contact Over Active Gate u Cobalt Interconnect (M0, M1) 14 u 1st Gen Foveros 3D Stacking u 2nd Gen EMIB 1272 1274 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 9Transisto
Slide 10: Process learnings: balance schedule, performance, power, cost
Transistor efficiency (Perf / W) LEARNINGS Balance between schedule, performance, power, cost 10 14 1272 1274 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 10Transistor efficiency (Perf / W) LEARNINGS Balance between schedule, performance, power, cost 10 14 1272 1274 2014 2015 2016 2017 2018 201
Slide 11: Intra-node advancement opportunity
Transistor efficiency (Perf / W) LEARNINGS Balance between schedule, performance, power, cost Significant opportunity for intra-node advancement 10 >20% Increase 14++ 14+ 14 1272 1274 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 11Transistor efficiency (Perf / W) LEARNINGS Balance between sched
Slide 12: Value in maintaining mix of nodes
Transistor efficiency (Perf / W) LEARNINGS Balance between schedule, performance, power, cost 10++ Significant opportunity for intra-node advancement 10+ 10 Value in maintaining mix of nodes 14++ Ease-of-design accelerates 14+ innovation 14 1274 1272 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023
Slide 13: 7nm and EUV roadmap
Transistor efficiency (Perf / W) 7++ 7+ 7 u 2x scaling 10++ u Planned intra-node optimizations 10+u 4x Reduction in design rules u EUV 10 u Next-gen Foveros & EMIB packaging 14++ 14+ 1276 14 1274 1272 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 13Transistor efficiency (Perf / W) 7++ 7+ 7 u 2x
Slide 14: 10nm shipping in June; 7nm progressing to plan
Transistor efficiency (Perf / W) One ML of scaling & performance start of node + one ML performance intra-node 7++ 7+ Multi-chip SoC construction for non-compromise performance 7 10++ Radical design simplification 10+ accelerates innovation 10 10nm shipping in June, multiple 14++ products through 20
Slide 15: Ice Lake shipping in June
IPU R Core Core I DISPLAY D N D G Core Core R Shipping in June Approx. Graphics Performance 2X TYPE C AI Performance 2.5X – 3x GT Video Encode 2x Wireless Speeds 3x OPIO Disclaimer: Results are approximate and have been estimated or simulated as of April 2019 using Intel internal analysis or archite
Slide 16: Multiple product launches through 2019 and 2020
Shipping in June IPU R Multiple Product Launches Core Core I DISPLAY D Across Entire Portfolio Through 2019 and 2020 N D G Core Core R AI Inference Xeon CPU GP-GPU TYPE C FPGA 5G/Networking… GT OPIO 16Shipping in June IPU R Multiple Product Launches Core Core I DISPLAY D Across Entire Portfolio Thro
Slide 17: Xe architecture GP-GPU using Foveros, launch in 2021
e X Architecture-Based GP-GPU using Foveros for Datacenter AI & HPC Launch in 2021 17e X Architecture-Based GP-GPU using Foveros for Datacenter AI & HPC Launch in 2021 17
Slide 18: Software unlocks orders of magnitude of performance
For every order of magnitude performance from new hardware, there is >2 orders of magnitude unlocked by software Raja Koduri Chief Architect, SVP Intel Architecture, Graphics and Software 18For every order of magnitude performance from new hardware, there is >2 orders of magnitude unlocked by softwa
Slide 19: Example 1: Java runtime optimizations
Example 1: Java runtime optimizations 6X 6 x 4X 2X 1 x 0X JDK9 JDK8 For more complete information about performance and benchmark results, visit www.intel.com/benchmarks. Performance results are based on testing as of dates shown in 19 configuration and may not reflect all publicly available securit
Slide 20: Example 2: Persistent memory stack optimizations
Example 2: Persistent memory complete stack optimizations 8X 8.1 x 6X 4X 2X 1 x 0X SSD Storage Intel Optane™ DCPMM +software For more complete information about performance and benchmark results, visit www.intel.com/benchmarks. Performance results are based on testing as of dates shown in 20 configu
Slide 21: Example 3: Deep Learning Boost
Example 3: Deep Learning Boost 28 x 20X 15X 10X 5X 1 x 0X Hardware + Software Base Hardware For more complete information about performance and benchmark results, visit www.intel.com/benchmarks. Performance results are based on testing as of dates shown in configuration and may not reflect all publi
Slide 22: Per core performance advantage
Per core performance advantage Data Analytics Java (1.9x) Web (2.1x) Browsing (1.7x) High Performance Compute Networking (1.9x) (2.0x) Productivity (1.6x) Deep Learning Gaming Content (1.4x) Creation (10.3x) (2.5x) For more complete information about performance and benchmark results, visit www.inte
Slide 23: Intel software scale and developer ecosystem
>15,000 software engineers #1 contributor to Linux kernel; >1/2 million lines of code modified each year > 100 operating systems optimized top three contributors to Chromium OS >10,000 high touch customer deployments top 10 contributor to Openstack >12 million developers For more complete informatio
Slide 24: CPU architecture and Intel software scale
CPU Architecture 24 Intel Software scaleCPU Architecture 24 Intel Software scale
Slide 25: One architecture
One Architecture 12 million developers 25One Architecture 12 million developers 25
Slide 26: Developers across cloud, GPU, AI and native
Cloud One GPU AI Architecture Native 8 million 1 million 100K developers developers developers 12 million developers 26Cloud One GPU AI Architecture Native 8 million 1 million 100K developers developers developers 12 million developers 26
Slide 27: One GPU AI architecture
One GPU AI Architecture 27One GPU AI Architecture 27
Slide 28: Diverse mix of scalar, vector, matrix and spatial architectures
“The future is a diverse mix of Scalar, Vector, Matrix and Spatial CPU GPU architectures deployed in CPU, GPU, FPGA and Accelerator AI FPGA sockets…” Intel Arch day, Dec ‘2018 28“The future is a diverse mix of Scalar, Vector, Matrix and Spatial CPU GPU architectures deployed in CPU, GPU, FPGA and Ac
Slide 29: CPU, GPU, AI and FPGA
CPU GPU GPU AI AI FPGA 29CPU GPU GPU AI AI FPGA 29
Slide 30: CPU, GPU, AI and FPGA
CPU GPU AI FPGA 30CPU GPU AI FPGA 30
Slide 31: Competitor comparison across CPU, GPU, AI, FPGA
CPU GPU AI FPGA GPU CPU GPU Competitor 2 Competitor 1 31CPU GPU AI FPGA GPU CPU GPU Competitor 2 Competitor 1 31
Slide 32: Simple, scalable, open, one developer experience
simple and scalable open one developer experience 32simple and scalable open one developer experience 32
Slide 33: Coming soon to developers in Q4 2019
Coming soon to a developer near you in Q4 2019 33Coming soon to a developer near you in Q4 2019 33
Slide 34: Data Center, Network, Intelligent Agents
Data Center Network Intelligent Agents 34Data Center Network Intelligent Agents 34
Slide 35: Data center: compute diversity
COMPUTE DIVERSITY Intel® MKL-DNN OpenVINO SPDK (Storage) Intel® Security (AI) (AI) DPDK (Network) Libraries - DC software Intel® Threat Intel® Security Detection Tech SGX Card Memory Encryption Ultra Path Interconnect Interconnect Highest Native Memory DDR Bandwidth Intel® Intel® Speed Intel® Worklo
Slide 36: Intelligent agents building blocks
INTELLIGENT AGENTS software Security Interconnect Memory XPU Architectures PROCESS & Packaging 36INTELLIGENT AGENTS software Security Interconnect Memory XPU Architectures PROCESS & Packaging 36
Slide 37: PC in mobile form factor
INTELLIGENT AGENTS PC in Mobile form factor – 12x12x1 37INTELLIGENT AGENTS PC in Mobile form factor – 12x12x1 37
Slide 38: Intelligent agents: chipset and package
INTELLIGENT AGENTS Chipset PACKAGE Power Delivery Ultra low power logic - P1222 38INTELLIGENT AGENTS Chipset PACKAGE Power Delivery Ultra low power logic - P1222 38
Slide 39: Scalable 3D silicon interconnect
INTELLIGENT AGENTS Scalable 3D silicon interconnect BASE Ultra low-power: 0.15 pico Joules / bit High bandwidth: 2-3X 2.5D interposer PACKAGE Scalable power delivery: 3W-1KW High yield process for die stacking 39INTELLIGENT AGENTS Scalable 3D silicon interconnect BASE Ultra low-power: 0.15 pico Joul
Slide 40: 10nm compute with Foveros hybrid architecture
INTELLIGENT AGENTS 10 nm process compute foveros Hybrid architecture: Core + Atom Thermal solution to enable 3D stacking BASE PACKAGE 40INTELLIGENT AGENTS 10 nm process compute foveros Hybrid architecture: Core + Atom Thermal solution to enable 3D stacking BASE PACKAGE 40
Slide 41: POP DRAM integration
INTELLIGENT AGENTS POP DRAM integration with 1 mm Z-height COMPUTE foveros BASE PACKAGE 41INTELLIGENT AGENTS POP DRAM integration with 1 mm Z-height COMPUTE foveros BASE PACKAGE 41
Slide 42: Lakefield hybrid architecture and power improvements
INTELLIGENT AGENTS OpenVINO software POP DRAM UFS Inline Boot from UFS VBS Security Encryption COMPUTE UFS 3.0 USB 3.0 MIPI CSI2 Interconnect foveros POP DRAM Memory BASE H y b R I d A R C H I T E C T U R E XPU Architectures GEN11 Graphics Sunny Cove CPU Tremont CPU PACKAGE Foveros 3D Integration PR
Slide 43: Data drives extraordinary opportunities for growth
Data drives extraordinary opportunities for growth Intel products & methods targeted to win data-centric growth with six pillar innovation model You will see this in our product leadership 43Data drives extraordinary opportunities for growth Intel products & methods targeted to win data-centric grow
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Slide 45: Performance and configuration notices
Performance results are based on testing as of dates shown in configuration and may not reflect all publicly available security updates. See configuration disclosure for details. No product or component can be absolutely secure. Software and workloads used in performance tests may have been optimize
Slide 46: Xeon performance configuration disclosures
nd 2 Gen Intel® Xeon Scalable Processors up to 28X AI Performance: Based on Intel internal testing: 28x performance improvement based on Intel® Optimization for Café ResNet-50 inference throughput performance on Intel® Xeon® Scalable Processor. 28x inference throughput improvement on Intel® Xeon® Pl
Slide 47: Lakefield configuration disclosures
Approx. 10x Lakefield Standby SoC Power Improvement: Estimated or simulated as of April 2019 using Intel internal analysis or architecture simulation or modeling. Vs. Amber Lake. Approx. 1.5x-2x Lakefield Active SoC Power Improvement: Estimated or simulated as of April 2019 using Intel internal anal
Slide 48: Benchmark and optimization notices
Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors