Asml Holding Nv · EURONEXT:ASML
Asml Holding Nv — Investor Day (September 2021)
42 slides from Asml Holding Nv's investor day presentation, Sep 30, 2021
Slide 1: Technology Strategy to Drive Moore's Law into Next Decade
Technology Strategy to Drive Moore’s Law into Next Decade Martin van den Brink President and Chief Technology Officer
Slide 2: Technology strategy: key messages
Technology strategy Holistic Lithography roadmap is driven by our unique Key messages patterning control solutions that deliver customer value viaSlide 2 29 Sept. 2021 improved on product performance. • Moore’s Law is alive and well! Industry innovation • ASML’s comprehensive product portfolio is al
Slide 3: Moore's Law evolution and customer roadmap
• Moore’s Law evolution and customer roadmap ASML’s strategic priorities 3
Slide 4: Significant device innovation in logic ahead of us
Significant device innovation in logic ahead of us scaling roadmap continues to 1 nm and beyond Slide 4 29 Sept. 2021 3 nm 2 nm1,5 nm1 nm and beyond PP: 44-48, MP: 21-24 PP: 40-44, MP: 18-21PP: 40-44, MP: 18-21PP: 38-42, MP: 15-18 BPR BPR FinFET Nanosheets, BPR Forksheets, VHV std cell arch. CFET, B
Slide 5: Innovation is not limited to device level
Innovation is not limited to device level TSMC’s system roadmap to >300 B transistors Slide 5 29 Sept. 2021 WoW: Wafer on Wafer CoWoS: Chip on Wafer on Substrate HBM: 3D High Speed MemoryRDL: Re Distribution Layer SOC: System on Chip CoW: Chip on Wafer FPGA: Field Programmable Grid ArrayInFo: Integr
Slide 6: Innovation is not limited to device level
Innovation is not limited to device level TSMC’s system roadmap to >300 B transistors Slide 6 29 Sept. 2021 WoW: Wafer on Wafer CoWoS: Chip on Wafer on Substrate HBM: 3D High Speed MemoryRDL: Re Distribution Layer SOC: System on Chip CoW: Chip on Wafer FPGA: Field Programmable Grid ArrayInFo: Integr
Slide 7: Moore's Law evolution: clock frequency saturated since 2005
Moore’s Law evolution: the next decade Traditional scaling metrics like clock frequency have been saturated since 2005 Slide 7 29 Sept. 2021 Public dataCustomerSpeculation 1020 projection Dennard Post Dennard 1018 scaling scaling 1016 1014 1012 1010 108 106 104 Clock Frequency1 [MHz] 102 1 1970 1980
Slide 8: Scaling of transistor and litho density continues this decade
Moore’s Law evolution: the next decade Scaling metric of transistor and litho density continues in this decade Slide 8 29 Sept. 2021 Public dataCustomerSpeculation 1020 projection DennardPost Dennard 1018 scalingscaling 1016 1014 1012 1010 Transistor density2 [#/mm2] 108 Device and layout optimizati
Slide 9: A system metric measuring energy and time efficiency
Moore’s Law evolution: the next decade A system metric measuring energy and time efficiency combined Slide 9 29 Sept. 2021 Energy-Efficient Performance for systems and devices defined as [1/J.s] If applied per single device: EEP = fc /e fc = clock frequency [s-1] e = the transistor switch energy [J]
Slide 10: Device Energy Efficient Performance growth saturated since 2005
Moore’s law evolution: the next decade Device Energy Efficient Performance growth been saturated since 2005 Slide 10 29 Sept. 2021 Public dataCustomerSpeculation 1020 projection DennardPost DennardSystem Energy 1018 scalingscaling Efficient Performance3 [1/J.s] 1016 From transistor to system scaling
Slide 11: System Energy Efficient Performance growth continues to 2040
Moore’s Law evolution: the next decade System Energy Efficient Performance growth 3x/2yrs continues to 2040Slide 11 29 Sept. 2021 Source: TSMC, Mark Liu, “Unleash the future of innovation” ISSCC, Feb 15, 2021. Public 11
Slide 12: From cost per transistor to cost of time and energy
Moore’s law evolution: the next decade From cost per transistor through density, to cost of time and energy through systems Slide 12 29 Sept. 2021 1020 Energy 1018 Performance3 1016 1014 tor Energy Performance2 1012 1010 tor density2 108 Device and layout optimizationLitho density2 106 (Contact Poly
Slide 13: System scaling to satisfy performance and energy needs
Moore’s law evolution: the next decade System scaling to satisfy the need for performance and energy consumption Slide 13 29 Sept. 2021 1020 System improvements System System Energy Efficient Performance3 1018 dominated by Transistor scaling scaling [1/J.s] 1016 From transistor to system scaling 101
Slide 14: AMD 3D chiplet gives 3.1-3.8 EEP improvement
AMD 3D chiplet gives an 3.1-3.8 EEP improvement By integrating memory with the processor in one package Slide 14 29 Sept. 2021 3x power reduction, 4-25% speed improvement Structural silicon 64MB L3 cache die Direct copper-to-copper bond Through Silicon Vias (TSVs) for silicon-to-silicon communicatio
Slide 15: System scaling to satisfy performance and energy needs
Moore’s law evolution: the next decade System scaling to satisfy the need for performance and energy consumption Slide 15 29 Sept. 2021 Public dataCustomerSpeculation 1020 projection System improvements System System Energy EfficientPerformance3 1018 dominated by Transistor scaling scaling [1/J.s] 1
Slide 16: Litho density scaling continues in this decade
Litho density scaling continues in this decade Overlay and Optical Proximity Correction errors shrink aggressively Slide 16 29 Sept. 2021 2x every 6 years Source: Average customer roadmap extended by ASML extrapolation May 2021, averaged with 2020 IRDS Roadmap Mustafa Badaroglu, “IRDS IFT – More Moo
Slide 17: Memory roadmap for the next decade
Memory roadmap for the nextdecade DRAM scaling below 10 nm and NAND stacking continues > 600 layers Slide 17 29 Sept. 2021 DRAM After 10 years NowChallenge<10 nm 1y 1z 1a1b1c1d0a NAND After 10 years NowChallenge>600layers 96 128 1762xx3xx4xx5xx6xx Source: Sk hynix, S.H.Lee, “Memory’s journey towards
Slide 18: Projection of lithography layers by technology
Projection of lithography layers by technology Slide 18 29 Sept. 2021 KrF Logic Layer stack 5 nm 3 nm 2 nm~1.5 nm1 nm KrF DRAM EUV – High-NA Layer stack 1A 1B 1C0A0BEUV ArFi ArF KrF KrF I-Line 3D-NAND Layer stack 176L 2xxL 3xxL4xxL5xxL 2021 ~2030 Source: ASML Corporate Strategy and Marketing estimat
Slide 19: Lithography layer count grows, driven by DUV and EUV
Projection of lithography layers by technology Lithography layer count grows, driven by DUV and EUV Slide 19 29 Sept. 2021 KrF Logic Layer stack 5 nm 3 nm 2 nm~1.5 nm1 nm KrF DRAM EUV – High-NA Layer stack 1A 1B 1C0A0BEUV DUV KrF 3D-NAND Layer stack 176L 2xxL 3xxL4xxL5xxL 2021 ~2030 Source: ASML Cor
Slide 20: Semiconductor and shrink roadmap: the next decades
Semiconductor and shrink roadmap: the next decades Slide 20 29 Sept. 2021 In the next decade, system scaling continues to fuel the need 10âµ 1962 of advanced semiconductor solutions where litho shrink component 10â´ remains key to improving circuit density and cost. per 1965 cost 10³ 10² 1970 manufa
Slide 21: ASML's strategic priorities
Moore’s Law evolution and customer roadmap • ASML’s strategic priorities 21
Slide 22: ASML's strategic priorities
ASML’s strategic priorities Slide 22 29 Sept. 2021 Strengthen â–ª Enhance execution capabilities to deliver performance, cost customer trust and robustness to customers needs Holistic litho and â–ª Build a leading position in edge placement error applications DUV â–ª Drive DUV performance and market
Slide 23: Our holistic portfolio is more important than ever
Our holistic portfolio is more important than ever Lithography scanner with Slide 23 29 Sept. 2021 advanced control capability Etch and deposition tools Process window Process window Prediction and Control Enhancement Optical proximity correction ieldStar E-beam Computational lithography Optical met
Slide 24: Our holistic portfolio is more important than ever
Our holistic portfolio ismore importantthanever Slide 24 29 Sept. 2021 EUV DUV High-NA Applications Public 24
Slide 25: Applications: strategic directions
Applications: strategic directions Deliver leading solutions for optical and e-beam metrology and inspection Slide 25 APPS 29 Sept. 2021 Customer Value ASML Apps product roadmap Capturing more wafer signatures to • Productivity improve robust on-wafer process control • Robust alignment schemes Nanom
Slide 26: E-beam inspection has inherent resolution advantage
E-beam inspection has inherent resolution advantage Increasing throughput through increasing parallelism with multibeam Slide 26 APPS 29 Sept. 2021 1000000 Min defect size for 2 nm node and below 100000 Optical Bright Field 10000 Inspection 1000 Gen 3 Multibeam (~2028) 100 Increased [mm²/hr] through
Slide 27: Metrology, Inspection & Patterning Control Roadmap
Metrology, Inspection & Patterning Control Roadmap Slide 27 APPS 29 Sept. 2021 2020 2021 202220232024 ³ 2025 Scanner Interfaces and Control Software Increasing Scanner Actuation (DUV and EUV), EPE Control Overlay Metrology Fast Stages, Multiple Wavelengths, Computational Metrology, YieldStar In-Devi
Slide 28: NXT:2050i in volume manufacturing at customers
NXT:2050i in volume manufacturing at customers DUV 20% overlay improvement, faster reliability and productivity ramp-up Slide 28 29 Sept. 2021 NXT:2050i Matched machineDedicated chuck overlay ~1.2 nmoverlay ~0.8 nm 6000 5,000 wafers per day in 18 days 200180 hours reliability in 13 weeks 180 5000 NX
Slide 29: DUV: Strategic directions
DUV: Strategic directions DUV Deliver leading solutions for advanced capabilities and higher productivity Slide 29 29 Sept. 2021 Customer value ASML DUV product roadmap Overlay Improve overlay (stability) especially •NXT:2100i with optics and alignment improvements for matching to EUV Productivity &
Slide 30: DUV product portfolio to support all market segments
DUV product portfolio to support all market segments DUV Slide 30 29 Sept. 2021 ength NA, Half pitch 202020212022202320242025 Continue innovationNXT:2000i on advanced NXT:2050i NXT platform for improved NXT:2100i imaging, overlay and productivity NEXT critical ArFi 1.35 NA,38 nm2.0 nm | 275wph1.5 nm
Slide 31: EUV 0.33 NA adoption enabled by platform maturity
EUV 0.33 NA adoption enabled by platform maturity in EUV high-volume manufacturing Slide 31 29 Sept. 2021 100% 3000 System output Max wafers per day (single system, weekly average) 95% 2500 90% Installed base system availability day 4 weeks moving average (end of period) 85% 2000 per 80% 1500 75% Av
Slide 32: EUV: strategic directions
EUV: strategic directions EUV Enabling cost-efficient scaling for advanced nodes Slide 32 29 Sept. 2021 Customer value using EUV ASML EUV product improvements Better device performance: simpler • Technology roadmap: per node (resolution), improve design and superior electrical imaging, overlay and d
Slide 33: High-NA to prevent cycle time and process complexity increase
High-NA to prevent cycle time and process complexity increase EUV like low NA did for immersion Slide 33 29 Sept. 2021 5 Insertionpreferred EUVEUV NANA 3 -- u. ) 0.330.55 (a. dependent) DUVEUV- 0.33NAEUV- 0.55NA complexity cycletime (product 3 0.33-NA insertion supports singleHigh-NA insertion oppor
Slide 34: High-NA EUV: strategic directions
High-NA EUV: strategic directions EUV Enabling cost-efficient scaling for next generation advanced nodes Slide 34 29 Sept. 2021 Customer value High-NA EUV ASML High-NA EUV product improvements 0.55 NA enables 1.7x smaller features and 2.9x increased density • Technology roadmap: per node (resolution
Slide 35: High-NA EUV is in the realization phase
High-NA EUV is in the realization phase EUV On multiple ASML and supplier locations Slide 35 29 Sept. 2021 Oberkochen, Germany optics system manufacturing facilities Veldhoven, the Netherlands, system bottom test EUV 0.55 NA optics Toulon, France, Frame milling Wilton, USA,system top test Public 35
Slide 36: EUV 0.55 NA expected to be added to EUV portfolio
EUV 0.55 NA is expected to be added to EUV portfolio EUV for high volume in 2025—2026 while continue improving the 0.33 NA platformSlide 36 29 Sept. 2021 2020 2021 202220232024 ³ 2025 0.33NA continuous imaging,NXE:3600Doverlay and productivity improvementsNXE:3800E in line NXE:4000F with customers a
Slide 37: Commonality across EUV, DUV & High-NA platforms
ST Commonality across EUV, DUV & High-NA platforms Slide 37 TRU Allows faster and more cost-effective innovation, production and maintenance 29 Sept. 2021 DUV EUV Alignment Sensor Common Technology Level sensor used in both Metrology DUV & EUV platform Wafer handling NXT (193 nm dry) Common Technolo
Slide 38: Maximizing customers' good wafers per day
ST Maximizing customers’ good wafers per day Slide 38 TRU Next to minimizing system down time 29 Sept. 2021 100% 100%100% System downtime System downtime serving according to customer needs standardized definition >97% Process-specific inefficiencies e.g., system down to meet customer specs, layer q
Slide 39: EUV is the most energy efficient solution
ST EUV is the most energy efficient solution Slide 39 TRU We expect net energy savings of more than 45% over alternative processes 29 Sept. 2021 EUV 0.33EUV 0.55 Electrical power reduction Electrical power reduction Immersion to EUV 0.33 productivity [wph] EUV 0.33 to EUV 0.55 at 220 wph Side wall A
Slide 40: Technology strategy: key messages
Technology strategy Holistic Lithography roadmap is driven by our unique Key messages patterning control solutions that deliver customer value viaSlide 40 29 Sept. 2021 improved on product performance. • Moore’s Law is alive and well! Industry innovation • ASML’s comprehensive product portfolio is a
Slide 41: Forward Looking Statements
Forward Looking Statements Slide 41 29 Sept. 2021 This presentation contains statements that are forward-looking, including statements with respect to expected industry and business environment trends including expected growth, outlook and expected financial results, including expected net sales, gr
Slide 42: ASML Small Talk 2021
ASML SMALL TALK 2021 42