Micron Technology, Inc. · NASDAQ:MU

Micron Technology — Flash Memory Summit 2008

19 slides from Micron Technology's conference presentation, August 2008

  1. Slide 1: Endurance Requirements for Next-Generation SLC NAND on Mobile Systems

    Endurance Requirements for Next-Generation SLC NAND on Mobile Systems Khurram Ismail Sr. Applications Engineer Micron Technology, Inc. ©2008 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products and/or sp

  2. Slide 2: Agenda

    Agenda ƒ Overview ƒ Program/erase cycling effects on NAND Flash ƒ How to minimize program/erase cycling effects ƒ Cycling of Flash devices in mobile systems • Usage models and their effects on NAND Flash • Usage models and how to predict the life of NAND Flash in a mobile system Santa Clara, CA USA

  3. Slide 3: Overview

    Overview ƒ In the mobile market, the SLC 100K endurance requirement has remained unchanged since the small-page NAND ƒ With the advancement in process nodes, it is becoming difficult to achieve 100,000 program/erase cycles ƒ As the densities/page sizes are increasing, should the requirement be same

  4. Slide 4: Program/Erase Cycling (Endurance)

    Program/Erase Cycling (Endurance) ƒ Program/erase (high I/O I/O I/O I/O voltage stress) cycles cause charge to be trapped in the dielectric ƒ Causes a permanent shift Damaged in cell characteristics—not Cells recovered by erase ƒ Observed as failed program or erase status ƒ Blocks that fail should b

  5. Slide 5: Data Retention

    Data Retention ƒ Charge loss/gain I/O I/O I/O I/O occurs on the floating gate over time; device threshold voltage trends to a quiescent Charge Loss level ƒ Cell is undamaged; block can be reliably erased and reprogrammed Note: Circuit structures and voltages are representative only. Details vary by

  6. Slide 6: Endurance and Data Retention

    Endurance and Data Retention ƒ There is a direct correlation in the number of cycles experienced by the NAND Flash and data retention Low cycled blocks have longer retention 5 yr High cycled blocks have Retention 2 yr shorter retention required (arbitrary time) 0.5 yr Block cycles 10 cyc 1K cyc 10K

  7. Slide 7: Maximizing Endurance and Data Retention

    Maximizing Endurance and Data Retention ƒ Robust wear-leveling mechanism ƒ Bad block management ƒ ECC Santa Clara, CA USA August 2008 7

  8. Slide 8: Good Wear-Leveling

    Good Wear-Leveling ƒ Makes sure that each block gets approximately equal amounts of Number of erases are even program/erase cycles across all blocks ƒ Elongates the life expectancy of the NAND Flash device ƒ Ensures more data can be stored before the bad block limits is reached Santa Clara, CA USA A

  9. Slide 9: Bad Wear-Leveling

    Bad Wear-Leveling ƒ Does not move around static data and only cycles the portion that is dynamic ƒ Shortens the life expectancy of NAND Most of the blocks don’t Flash device see erases ƒ Stores less data before the bad block limit is reached Santa Clara, CA USA August 2008 9

  10. Slide 10: Theoretical Expected Life of SLC NAND Flash

    Theoretical Expected Life of SLC NAND Flash ƒ Assumes cycling of 1GB daily until 100K Flash expected life through 100K cycles with daily 1GB storage cycles are reached 116.4 ƒ Nand Flash life(years) 140.0 120.0 Assumes that the 100.0 80.0 wear-leveling is perfect 60.0 58.2 40.0 20.0 0.9 1.9 3.7 7.5

  11. Slide 11: Theoretical Expected Amount of Cycles

    Theoretical Expected Amount of Cycles ƒ Taking the smallest density, Amount of Cycles requiredper density tostore 800000MB such as 64Mb, and multiplying this by 100K 120000 cycles, we get 800,000MB Program/Erase cycles 100000 100000 worth of data that can be 80000 cycled through 64Mb device 60000 50

  12. Slide 12: System Information

    System Information ƒ Lets examine some use cases on a mobile platform running with operating system 1 (OS1) with no wear-leveling and operating system 2 (OS2) with wear-leveling ƒ Both OSs use NAND Flash as a boot solution ƒ The file system resides inside the NAND Flash ƒ The wear-leveling also resi

  13. Slide 13: Use Cases

    Use Cases ƒ All use cases assume 1GB of data is cycled daily through NAND Flash device ƒ 256MB device is used; the endurance spec on this device is 100,000 program/erase cycles ƒ The use cases keep certain portions of the NAND Flash with static data ƒ The system is booted, and a test application is

  14. Slide 14: Use Case (OS1)

    Use Case 1 (OS1) Number of Erase per block ƒ 97% of NAND Flash filled 120000 with static data 100000 ƒ Test application creates random files with sizes 80000 No wear-leveling to ranging from 64KB to Number of erase the blocks with static data 1MB ƒ Bad; not all the good 60000 Number of erases 40000

  15. Slide 15: Use Case (OS1 To Be Collected)

    Use Case 2 (OS1 To Be Collected) Number of Erase per block ƒ 70% of NAND Flash filled 120000 with static data ƒ Test application creates 100000 random files with sizes No wear-leveling to the ranging from 64KB to Noumber of Erase 80000 blocks with static data 1MB 60000 Number of Erase ƒ Bad; not all

  16. Slide 16: Use Case (OS2)

    Use Case 1 (OS2) ƒ 97% of NAND Flash filled with static data ƒ Test application creates 1 file with fixed size ƒ Better; a lot of blocks see even amount of erases ƒ With this use case, the 256MB device will last 7 years, cycling 1GB daily ƒ Erase-to-write ratio is 1.79 Santa Clara, CA USA August 200

  17. Slide 17: Revised Expected Life of SLC NAND Flash (No Wear-Leveling)

    Revised Expected Life of SLC NAND Flash (No Wear-Leveling) Flash expected life through 100K cycles with daily 1GB storage ƒ This model assumes cycling of 1GB daily N a n d F la s h lif e ( y e a r s ) 7.0 6.3 until 100K cycles are 6.0 5.0 reached 4.0 3.2 ƒ 97% of NAND Flash 3.0 2.0 0.8 has static da

  18. Slide 18: Revised Expected Life of SLC NAND Flash (With Wear-Leveling)

    Revised Expected Life of SLC NAND Flash (With Wear-Leveling) Flash expected life through 100K cycles with daily 1GB storage ƒ This model assumes cycling of 1GB daily 27.7 N a n d F la s h l if e ( y e a r s ) 30.0 until 100K cycles are 25.0 20.0 reached 15.0 13.8 ƒ 97% of NAND Flash 10.0 3.5 has sta

  19. Slide 19: Conclusion

    Conclusion ƒ With wear-leveling and 1GB write daily, we get about 7 years on a 256MB device; is the 100K cycles really required ƒ On large page 1G, 2G, 4G SLC, the requirement should be reviewed ƒ From the initial data, 100K requirement looks like overkill Santa Clara, CA USA August 2008 19

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