Synopsys, Inc. · NASDAQ:SNPS
Synopsys — Technical Presentation (2021)
23 slides from Synopsys's technical presentation, 2021
Slide 1: Enablement, Evaluation and Extension of a CDM ESD Verification Tool for IC Level
2021 EOS/ESD Symposium Enablement, Evaluation and Extension of a CDM ESD Verification Tool for IC Level Christian Russ1, Kai Esmark1, Patrick Huff1, Jens Schneider1, Gernot Langguth1, Lena Zeitlhöfler2, Meruzhan Cadjan3, Yuri Feinberg3 1Infineon Technologies AG, Neubiberg, Germany 2Technical Univers
Slide 2: Purpose of this Work
Purpose of this Work n To share experiences in enabling a CDM verification tool for IC design n To evaluate this tool for its capability to confirm a detected physical failure n To extend the methodology of the tool for treatment of CDM-relevant inductances n To match pin-specific CDM-levels between
Slide 3: Outline
Outline n Introduction n Setup of CDM Verification Tool n CDM Case Study: Bus Line Inductance n Extended Tool Methodology: Automated Inductance Extraction n Comparison of CDM Levels: Tool vs. Experiments n Conclusions
Slide 4: Introduction (1): CDM Fails but no Explanation
Introduction (1): CDM Fails but no Explanation… L n 3-Million-transistor design, 130nm technology n Multiple gate oxide failures observed at core RX soon above target CDM level (500V, 6A) n Signals to RX do not cross domain border: intra-domain 24 n ESRA-CDM: uncritical differences in electric poten
Slide 5: Introduction (2): Intra-Domain Interface, Aggressor vs. Victim
Introduction (2): Intra-Domain Interface, Aggressor vs. Victim common vdd common gnd V gndd1v5 gndd1v5 digital core V gndd gndd bus vddd3v3 vddd1v5 A A V A sclk io io io io io io io ss si io io io io io io io gndd bus X-direction 2600um 1725um 1225um 0
Slide 6: Outline
Outline n Introduction n Setup of CDM Verification Tool n CDM Case Study: Bus Line Inductance n Extended Tool Methodology: Automated Inductance Extraction n Comparison of CDM Levels: Tool vs. Experiments n Conclusions
Slide 7: Setup and Principle of ESRA-CDM Tool
Setup and Principle of ESRA-CDM Tool n Technology base info Domain 1 Domain 2 n Layout (LVS-clean) R n Parasitic resistance extraction Aggressor n (vf)TLP curves of ESD elements ESD Victim ESD Vgs,max? n Distribution of initial CDM Icdm charges according to layout area n Circuit simulation of the ES
Slide 8: ESD Gate Oxide Limits for Victim Devices
ESD Gate Oxide Limits for Victim Devices 9.0 n Characterization by TLP and Vbd, positive vfTLP for tp=100ns à 1ns 8.5 power law fit 8.0 margin to 3-sigma margin n Focus on Gate-Source and actual Gate-Drain limits: Vgd=Vgs 7.5 CDM fail n Details on measurement Vbd (V) 7.0 levels techniques: see full
Slide 9: Outline
Outline n Introduction n Setup of CDM Verification Tool n CDM Case Study: Bus Line Inductance n Extended Tool Methodology: Automated Inductance Extraction n Comparison of CDM Levels: Tool vs. Experiments n Conclusions
Slide 10: CDM Case Study
CDM Case Study 6 500V FFT amplitude (a.u.) FFT 4 à current (A) 2 0 -2 -4 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1.0x108 1.0x109 1.0x1010 time (ns) frequency (Hz) n CDM center frequency around 1 GHz n Input parameter for inductive contribution of bus line
Slide 11: CDM Case Study - Bus Line Inductance
CDM Case Study - Bus Line Inductance Ansys HFSS simulation of VSS bus L ZR=0.24Ω/mm 10 ZL=2πfL=3Ω/mm Impedance (Ω/mm) Mtop d L=0.48nH/mm Mtop-1 W i ve 1 u ct n Ohmic resistance of top metals i nd t has decreased with technology ZL e ffec skin advancement 0.1 ZR resistive n Bus lines became narrower
Slide 12: CDM Case Study - Bus Line Inductance
CDM Case Study - Bus Line Inductance vf-TLP pad 2 pad 1 L R impedance of bus line ∆Vpeak=10V n Experimental demonstration of Voltage (V) impact of bus line inductance: n L=2mm n 600ps risetime pulse, 7A current n Inductive voltage peak ∆Vpeak=10V much larger than resistive voltage drop of 3V n Volta
Slide 13: Outline
Outline n Introduction n Setup of CDM Verification Tool n CDM Case Study ─ Bus Line Inductance ─ Modified Tool Setup n Extended Tool Methodology: Automated Inductance Extraction n Comparison of CDM Levels: Tool vs. Experiments n Conclusions
Slide 14: Extended Methodology: Automated Inductance Extraction
Extended Methodology: Automated Inductance Extraction n Inductance of straight conductor [Kalantarov]: l 𝜇(𝑙 2𝑙 1 𝐿= ln + 𝑓𝑜𝑟 𝑙 ≫ 𝑑, 𝑤 2π 𝑑+𝑤 2 n Implementation in ESRA-CDM to account for d w inductive effects in addition to ohmic effects nt * + 𝑉 * 𝑤𝑖𝑡ℎ 𝑉 rre 𝑉= 𝑉$') +,- $') =…
Slide 15: Localization of Highly Inductive Regions
Localization of Highly Inductive Regions vddd1v5 and gndd1v5 bridges from pad to core power density (W/um2) core mesh n Power density plot most effective way of displaying results n Bottleneck in metallization from pad ring to digital core mesh detected only by automated inductance extraction
Slide 16: Tool Enhancements for Treatment of Inductance
Tool Enhancements for Treatment of Inductance 24 map of electric potential in digital ground nets gndd and 22 gndd1v5, Icdm=7A, positive resistive 20 ) V (l only a it n e t 18 o inductive, p ci rt selected c e l regions digital core with 16 e gndd1v5 mesh victim aggressor ?VGND=11.8V 14 digital IOs
Slide 17: Analysis of Intra-Domain Issue on Chip Level (2)
Analysis of Intra-Domain Issue on Chip Level (2) 2.2A vddd3v3 L R Driver + vddd1v5 mesh ESD vddd1v5 0.7A 7A 3v3 1v5 buffer ESD ESD signal line Victim Aggressor 2.1A 2.4V Vg Icdm 0.6A s 2.0A 1.4A 9.4V 2.6A 4.8A gndd1v5 mesh 2.7A 3.2A package 2.4V gndd bus connection 0.2A 9.4V
Slide 18: Outline
Outline n Introduction n Setup of CDM Verification Tool n CDM Case Study: Bus Line Inductance n Extended Tool Methodology: Automated Inductance Extraction n Comparison of CDM Levels: Tool vs. Experiments n Conclusions
Slide 19: Comparison of CDM Levels: Tool vs. Experiments
B C Comparison D of CDM Levels: Tool vs. Experiments n i n i n i a a a m o m o m o n Pad-specific ESD robustness d d d example of discharge pad n Correlation CCTLP vs ESRA X-direction aggressor location Xa 0 CCTLP-experiment pin Xa (um) 4A 5A 6A 7A 8A 9A 10A 11A sclk 1182 pass pass pass pass pass n/
Slide 20: Comparison of CDM Levels: Tool vs. Experiments
Comparison of CDM Levels: Tool vs. Experiments n Correlation between failure current and 90% Vgs violation n Why 90%? ─ 0% = design limit of 6.0V ─ 90% above limit = 11.4V ─ Actual failure level > design limit ─ Voltage at victim: RC delays, top portion of voltage pulse contributes to actual gox bre
Slide 21: Design Improvements
Design Improvements n Small local metal straps between map of electric potential in ─ vddd1v5: bus ßà core mesh digital ground nets gndd and gndd1v5, Icdm=7A, positive ─ gndd1v5: bus ßà core mesh n Local interface protection at the receivers n Metal reinforcements: reduce inductance prevailing over
Slide 22: Outline
Outline n Introduction n Setup of CDM Verification Tool n CDM Case Study: Bus Line Inductance n Extended Tool Methodology: Automated Inductance Extraction n Comparison of CDM Levels: Tool vs. Experiments n Conclusions
Slide 23: Conclusions
Conclusions n CDM failure observed despite adherence of existing design rules n Gate oxide characterization down to nano-second range: careful relaxation of limits possible n Accounting for inductances in the layout: ─ Focus on inductances which are part of CDM discharge path ─ Several relevant loca