Asml Holding Nv · EURONEXT:ASML
Asml Holding Nv — Investor Day (November 2007)
40 slides from Asml Holding Nv's investor day presentation, Nov 2, 2007
Slide 1: Investor Day: Long-Term Lithography Market Potential
Investor Day Long-Term Lithography Market Potential Dr. Antonio Mesquida Küsters, Director of Market Intelligence London, November 2nd 2007 <file name> 02.11.2007 / Slide 1 Confidential <version 00> <author>
Slide 2: Safe Harbor
Safe Harbor “Safe Harbor” Statement under the U.S. Private Securities Litigation Reform Act of 1995: the matters discussed in this presentation may include forward-looking statements that are subject to risks and uncertainties including, but not limited to: economic conditions, product demand and se
Slide 3: Contents
Contents Introduction Long-term market potential (2006 – 2012) ASML’s Lithography Demand Simulation Model Some examples of simulated market scenarios Summary & Conclusions 02.11.2007 / Slide 3
Slide 4: Introduction
Introduction Driven by a relatively stable market since the last down-turn in 2001-02, ASML has increased YoY revenues since then, mainly driven by: Increased CapEx spending, driven by strong memory investments Increased spending share of lithography segment out of total CapEx Increased mark
Slide 5: Contents
Contents Introduction Long-term market potential (2006 – 2012) ASML’s Lithography Demand Simulation Model Some examples of simulated market scenarios Summary & Conclusions 02.11.2007 / Slide 5
Slide 6: ASML has developed a comprehensive market simulation model
In order to better estimate long-term lithography demand, ASML has developed a comprehensive market simulation model As part of the market intelligence activities, ASML does implement long- term scenario analysis on a regular basis for the following reasons: Mid- to long-term product roadmap dec
Slide 7: Long-Term Demand Simulation: Basic Model Structure
Long-Term Demand Simulation: Basic Model Structure* Input parameter Interim result / Final result IC Demand IC unit demand ⇒ IC unit demand x Application ⇒ IC Units by application x Node distribution ⇒ IC Units by application by node x Wafer size distribution ⇒ IC Units by application by node by waf
Slide 8: Simulation model takes into account installed base and capacity obsolescence
The simulation model takes into account both installed equipment base and (200 mm) capacity obsolescence Example about how simulation model calculates litho demand: Segment A, Wavelength B, Wafer Size C Installed base Required installed base Additional demand Tool obsolecence 1200 1100 LItho Tool De
Slide 9: Selected IC market segmentation for simulation model
Selected IC market segmentation for simulation model better displays the diversity of layer stacks driving litho demand Segmentation @ Litho Demand Main IC segment IC Subsegment (detailed) Simulation Model DRAM DRAM Memory NAND FLASH NAND NOR FLASH NOR µ-Processors (MPU) MPU Micro µ-Controllers (MCU
Slide 10: Expected IC unit node distribution by year
For each segment, the expected timing & distribution of IC units by year is continuously updated using 3rd party estimates DRAM Segment: Expected IC Unit Node Distribution by Year 80% 28 nm 32 nm 38 nm 45 nm 55 nm 65 nm 80 nm 90 nm 0.11 µm 0.13 µm 0.15 µm 0.18 µm 70% 60% IC distribution by node [% o
Slide 11: Wafer split between 200 and 300 mm
Wafer split between 200 vs. 300 mm taken into account for each segment, thus defining timing & volumes for tool obsolescence Example of 200 versus 300 mm Exposed Area distribution over time: DRAM segment 100% Area distribution by wafer size [% of total exposed area] 90% 80% 70% 60% 50% 200 mm 40% 30
Slide 12: Die sizes calculated using smoothed trend lines
Die sizes are calculated using smoothed trend lines of historic values for each IC segment Expected Average Die Size by Main IC Segment between 2000 and 2012 250 DRAM NAND NOR MPU LOGIC+MCU+DSP ANALOG OTHER 200 Die Size [mm2] 150 100 50 0 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2
Slide 13: Average layer stack calculated for each node and segment
“Average” layer stack calculated for each node and segment, based on weighted calculation* from customer layer stacks DRAM lithography layer stack by process node Extrapolated 50 40 5 5 6 11 11 6 6 EUV 30 9 4 ArFi-DPT Layers 7 5 3 7 5 ArFi 4 ArF 20 9 12 12 13 17 18 18 KrF 10 I-line 10 13 15 14 14 DP
Slide 14: Litho shrink roadmap in Base Case scenario
Litho shrink roadmap, as used in Base Case simulation scenario, does follow internal roadmaps of key customers Expected timing for lithography shrink roadmap of main IC segments Year 1 DRAM NAND LOGIC 2 2007 65 nm 55 nm 45 nm 2008 55 nm 45 nm 2009 38 nm 38 nm 2010 45 nm 2D-shrink 32 nm 3D-shrink pat
Slide 15: Model simulates lithography market demand
The Model is simulating the lithography market demand based on IC manufacturing technology & market trends The model shows the expected litho tool demand by segment assuming a certain IC volume growth The model will always select the cheapest tool, which meets the technical requirements for a sp
Slide 16: Contents
Contents Introduction Long-term market potential (2006 – 2012) ASML’s Lithography Demand Simulation Model Some examples of simulated market scenarios Summary & Conclusions 02.11.2007 / Slide 16
Slide 17: Technology and market-based scenarios
Apart from Base Case Scenario, 2 Technology & 2 Market-based scenarios have been selected to display boundaries of future litho demand Main technology 3D versus 2Dshrink for Scenario name Assumption IC growth choice NAND History: WSTS; 2007‐2008 DPT preferred over fcst.: Gartner (memory), Avg. NAND
Slide 18: Expected IC unit growth in Base Scenario
Expected IC unit growth, as used in Base Scenario, based on both forecasted (2007-08) and calculated (2009-12) data for each IC segment IC UNIT FORECAST: BASE CASE SCENARIO IC UNITS by segment [Bio. Units] 2006 2007 2008 2009 2010 2011 2012 DRAM 8.0 11.9 14.0 16.0 18.2 20.7 23.5 NAND 1.8 2.7 4.1 5.1
Slide 19: Base Case: lithography system demand in units
Base Case Scenario*: Due to conservative model assumptions (e.g. ideal market efficiency), demand expected to be @ 500-600 unit level WW Lithography Demand Simulation (2006 ‐ 12): Base Case Scenario "193i extension" Unit Split by Wavelength 800 iline KrF ArF ArFi EUV 700 Lithography System Demand [U
Slide 20: Base Case: lithography system revenue
Base Case Scenario*: regardless of stable unit demand, litho market expected to grow for the next 5 years due to tool ASP increase WW Lithography Demand Simulation (2006 ‐ 12): Base Case Scenario "193i extension" Revenue Split by Wavelength [Mio. €] 11,000 iline 10,000 KrF .0 % = 13 6-12 9,000 ArF 0
Slide 21: Lithography market size: simulation vs Gartner history
Base Case Simulation does predict CAGR of 13,0% between 2006 & 2012, i.e. very well in line with Gartner’s historic number of 14,2% Comparison of Step & Scan Lithography Market Size: Historic numbers (i.e. based on Gartner) Dataquest vs. Simulation Results 100000 Gartner Simulation Expon. (Gartner)
Slide 22: Base Case: revenue by IC segment
Base Case Scenario*: Market growth expected to come from DRAM, NAND & LOGIC segments, i.e. driven by shrink & IC unit growth WW Lithography Demand Simulation (2006 ‐ 12): Base Case Scenario "193i extension" Revenue Split by IC Segment 11,000 DRAM NAND LOGIC+MCU+DSP MPU ANALOG NOR OTHER 10,000 9,000
Slide 23: 200 mm tool obsolescence in DRAM
Model predicts significant 200 mm memory capacity obsolescence in DRAM Base Case Scenario: Simulated 200 mm Tool Obsolescence by Wavelength DRAM Segments 350 iline KrF ArF 300 200 mm obsolete Tools [Units] 250 Simulated number of obsolete 200 mm DRAM tools (i.e. 715 units) does correlate 200 very we
Slide 24: Scaling options influencing litho technology and volume
Different scaling options influencing litho technology & volume 3 scenarios have been evaluated projecting future technology needs Decreased process R&D & litho equipment complexity and ASP Cost/volume Increased cost per function & litho volume Traditional 2D 2D scaling through process “Aggressive 3
Slide 25: Scenario Aggressive 3D-scaling
Technology Scenario* “Aggressive 3D-scaling” yields a slightly higher tool demand & revenue outlook than Base Case, especially in 2012 WW Lithography Demand Simulation (2006 ‐ 12): Scenario "Aggressive 3D‐scaling" WW Lithography Demand Simulation (2006 ‐ 12): Scenario "Aggressive 3D scaling" Unit Sp
Slide 26: NAND segment growing fastest in exposed area
Technology NAND segment growing fastest in terms of exposed area 3D-shrink expected to have positive impact on NAND litho demand Exposed Silicon Area vs. Cummulative Litho Revenue by IC Segment (2006-2012) NAND 2D versus 3D-shrink comparison 28,000 Bubble size indicates Segment exposed area Cumulati
Slide 27: Scenario Aggressive EUV ramp-up
Technology Scenario* “Aggressive EUV ramp-up”: if NAND makers select EUV over double patterning after 2010, tool demand would grow fast WW Lithography Demand Simulation (2006 ‐ 12): Scenario "Aggressive EUV ramp‐up" WW Lithography Demand Simulation (2006 ‐ 12): Scenario "Aggressive EUV ramp‐up" Unit
Slide 28: Comparison of technology scenarios: revenue by wavelength
Technology Comparison of technology scenarios*: despite a significant difference in mix, only minor impact on overall revenue outlook WW Lithography Demand Simulation (2006 ‐ 2012): Comparison of TECHNOLOGY Scenarios Revenue Split by Wavelength 13,000 iline KrF ArF ArFi EUV 12,000 11,000 Lithography
Slide 29: Comparison of technology scenarios: revenue by IC segment
Technology Comparison of technology scenarios*: revenue outlook by IC segment mainly driven by IC growth, not by the technology mix WW Lithography Demand Simulation (2006 ‐ 2012): Comparison of TECHNOLOGY Scenarios Revenue Split by IC Segment 13,000 DRAM NAND LOGIC+MCU+DSP MPU ANALOG NOR OTHER 12,00
Slide 30: Slow-down in IC unit growth scenario
Market For the scenario “slow-down in IC unit growth”, we assume that all IC segments would be equally affected IC UNIT FORECAST: SLOW DOWN SCENARIO 2006 2007 2008 2009 2010 2011 2012 DRAM 8.0 11.9 14.0 15.9 17.8 19.8 21.9 NAND 1.8 2.7 4.1 5.1 6.0 7.2 8.2 NOR 3.7 3.7 4.3 4.7 4.9 5.1 5.3 MPU 0.4 0.4
Slide 31: Scenario Slow-down of IC growth
Market Scenario* “Slow-down of IC growth”: Even with a reduction of IC growth to ∼8% by 2012, litho market size would be close to € 9 Bln WW Lithography Demand Simulation (2006 ‐ 12): Scenario "Slow‐down in IC growth" WW Lithography Demand Simulation (2006 ‐ 12): Scenario "Slow‐down in IC growth" Un
Slide 32: Memory expansion fuelling appetite for NAND and DRAM
Rapid expansion of memory for PC & consumer products fuelling insatiable appetite for NAND & DRAM IC’s⇒ unit growth expected to accelerate Game MP3 Cell Phone Console 2.4x 14x 3x 2004 2007 2004 2007 674M Cell Phone 1000M Cell Phone 2004 2007 30M Game Console 40M Game Console 1 PSRAM per unit 1 PSRAM
Slide 33: Acceleration of IC unit growth scenario
Market In our best-case scenario, i.e. “acceleration of IC unit growth”, only NAND volumes are higher, as compared to base case IC UNIT FORECAST: ACCELERATION IC UNIT GROWTH IC UNITS by segment [Bio. Units] 2006 2007 2008 2009 2010 2011 2012 DRAM 8.0 11.9 14.0 16.0 18.2 20.7 23.5 NAND 1.8 2.7 4.1 6.
Slide 34: NAND MB demand by end-user application
Market “Acceleration of IC unit growth” scenario assumes strong future demand for NAND IC’s in mobile apps., e.g. SSD in NB PCs* N AND M B dem and by end-user application (2000-2011) 45000 Video & Lifestyle Data Imaging Audio Computing Storage 40000 Digit al Cam era 35000 N A N D d e m a n d [B i o
Slide 35: Scenario Acceleration of IC growth
Market Scenario* “Acceleration of IC growth”: if NAND IC units keep increasing @ +30% YoY through 2012, litho market could reach € 12 Bln level ! WW Lithography Demand Simulation (2006 ‐ 12): Scenario "Acceleration of IC growth" WW Lithography Demand Simulation (2006 ‐ 12): Scenario "Acceleration of
Slide 36: Comparison of market scenarios: revenue by wavelength
Market Comparison market scenarios*: IC unit growth has significant impact on tool demand, thus having strong effect on revenue outlook WW Lithography Demand Simulation (2006 ‐ 2012): Comparison of MARKET Scenarios Revenue Split by Wavelength 14,000 iline KrF ArF ArFi EUV 13,000 12,000 Lithography S
Slide 37: Comparison of market scenarios: revenue by IC segment
Market Comparison market scenarios*: Long-term unit growth of NAND segment will be key in defining lithography market size WW Lithography Demand Simulation (2006 ‐ 2012): Comparison of MARKET Scenarios Revenue Split by IC Segment 14,000 13,000 DRAM NAND LOGIC+MCU+DSP MPU ANALOG NOR OTHER 12,000 Lith
Slide 38: Contents
Contents Introduction Long-term market potential (2006 – 2012) ASML’s Lithography Demand Simulation Model Some examples of simulated market scenarios Summary & Conclusions 02.11.2007 / Slide 38
Slide 39: Summary & Conclusions
Summary & Conclusions ASML has developed a comprehensive market model that translates IC unit growth into lithography demand taking into account several parameters, including lithography layer stacks, node timing and distribution, wafer size, tool obsolescence, etc. Model assumes perfectly effic
Slide 40: Commitment
Commitment 02.11.2007 / Slide 40