Uniquest Corporation · KRX:077500

Uniquest — Technical Presentation (September 2002)

70 slides from Uniquest's technical presentation, September 2002

  1. Slide 1: Next Generation Network Processor & Development Tools

    Next Generation Network Processor & Development Tools YS Kim Field Application Engineer Sep 2002 Page 1

  2. Slide 2: Agenda

    Agenda  Overview  What is a Network Processor?  Overview of the IXP1200 Family  Introduction to "IXP2400"  Introduction to "IXP2800"  Development Tools  Example Intel® IXA Applications  Summary Page 2

  3. Slide 3: Agenda

    Agenda  Overview  What is a Network Processor?  Overview of the IXP1200 Family  Introduction to "IXP2400"  Introduction to "IXP2800"  Development Tools  Example Intel® IXA Applications  Summary Page 3

  4. Slide 4: Intel's Strategic Architectures

    Intel’s 4 Strategic Architectures Page 4

  5. Slide 5: Agenda

    Agenda  Overview  What is a Network Processor?  Overview of the IXP1200 Family  Introduction to "IXP2400"  Introduction to "IXP2800"  Development Tools  Example Intel® IXA Applications  Summary Page 5

  6. Slide 6: What is a Network Processor?

    What is a Network Processor?  Flexible Programming Capability – Minimal fixed format packet/cell states between processing stages – Software controlled state maintenance & manipulation  Performance capable of deep packet/cell inspection at wire rates  Highly integrated Processor – Includes memory

  7. Slide 7: Sophisticated Packet Analysis

    Sophisticated Packet Analysis Ethernet Preamble Ethernet Header New tasks require looking deeper Ethernet Preamble Start Frame into the packet… Destination MAC Address  Ethernet Switching Dest MAC Addr Source MAC Addr Source MAC Address  Simple Quality of Service Length or Type – 802.1p & Q (Type

  8. Slide 8: How the Network Processor Processing Packets

    How the Network Processor Processing Packets Page 8

  9. Slide 9: Agenda

    Agenda  Overview  What is a Network Processor?  Overview of the IXP1200 Family  Introduction to "IXP2400"  Introduction to "IXP2800"  Development Tools  Example Intel® IXA Applications  Summary Page 9

  10. Slide 10: What is the IXP1200?

    What is the IXP1200?  Offers the best of ASICs & RISC Processors – Dedicated, programmable network processor engines – Integrated RISC CPU core for mgmt & control – Unmatched combination of performance, flexibility, and opportunity for differentiation  Centerpiece of the Internet Exchange Family –

  11. Slide 11: IXP1200 NP enables flexible product development

    IXP1200 NP enables flexible product development  Very Low Power Parallel Processor Architecture with 7 232 MHz RISC processors  Hardware Based StrongARM Core PCI Multithreading on 6 RISC engines - Cost Effective  Distributed Data Storage Arch Supports Very Simple SRAM SDRAM Programming Model  Ac

  12. Slide 12: IXP1200 Block Diagram

    IXP1200 Block Diagram 64 Bit SDRAM Controller Micro- Engine 0 32 Bit PCI Micro- Interface Engine 1 Hash Engine Micro- Engine 2 IX Bus 16K B Interface 64 Bit Instruction StrongARM Cache Micro- Core Engine 3 Scratch Pad (232 MHz) 8KB SRAM Data Cache Micro- Engine 4 1 K B Mini- Data Cache Micro- Engine

  13. Slide 13: IXP1200 Features

    IXP1200 Features  Microengines & Processor – 232 MHz Applications CPU – 6 Microengines (Optional) – 2K control store on all uEng.  SRAM Interface PCI Bus – 32-Bit @ 116 MHz – “Slow Side” Ready Signal IXP1200 SRAM Network – 8 MB Max Processor  SDRAM Interface SDRAM – 64-Bit @ 116 MHz Flash – 256 M

  14. Slide 14: IXP1200 Target Applications

    IXP1200 Target Applications  Multi Service Switches  Voice over IP blades  DSLAMs  VPN Gateways  3G Base Station transceivers Page 14

  15. Slide 15: Intel IXDP1200 Advanced Development Platform

    Intel® IXDP1200 Advanced Development Platform Page 15

  16. Slide 16: IXDP1200 Platform Features

    IXDP1200 Platform Features • Consists of four sub-systems: 1. IXM1200 Network Processor Base Card 2. IXD4501 LAN I/O Option Card 3. IXD4521 WAN I/O Option Card – Each Option Card attaches to IXM1200 (1 Option Card per Base Card)) 4. Eight slot 6U CompactPCI Chassis – Includes ESC3306 System Controll

  17. Slide 17: IXA Software Development Kit

    IXA Software Development Kit  Pre-installed on the IXDP1200 Advance Development Platform – Diagnostics – VxWorks* – Tornado 2 – IXA SDK Volume I – Windows NT Integrated Development Environment / Example Code  Software development environment for the IXP1200 Network Processor Family – Extensive sof

  18. Slide 18: IXA SDK 2.0 Development Advantage

    IXA SDK 2.0 Development Advantage  IXA SDK 2.0 New Features: 1. Enhanced Workbench / Transactor - advanced graphical simulation, profiling and debugging IDE – Enables faster prototyping, intuitive optimization, supports data plane and control plane applications 2. Full support for choice of popular

  19. Slide 19: ATM/OC-3 to Fast Ethernet IP Router Example Design

    ATM/OC-3 to Fast Ethernet IP Router Example Design  Runs on the IXDP1200 Advanced Development Platform  Demonstrates full duplex ATM-Ethernet protocol conversion over dual OC-3 links.  Supports software-based Segmentation and Reassembly (SAR) of ATM cells  Includes software-based Cyclic Redundan

  20. Slide 20: Microengine C language

    Microengine C language  Programming abstraction for simplified Microengine coding. – Microengine C: dest = (a + b) - c – Microcode alu [ dest1, a, +, b] alu [ dest2, dest1, -, c]  Microengine C and Compiler: – Subset of ANSI C language and ANSI C library – Optimizes code for the Microengines – Mic

  21. Slide 21: Embedded OS Support

    Embedded OS Support  VxWorks support (Volume I of IXA SDK 2.0) – 3rd party (WindRiver*) supplied VxWorks* – 60 day trial version of Wind River Systems – Tornado* toolchain – VxWorks BSPs  Linux support (Volume II of IXA SDK 2.0) – 3rd party (LynuxWorks*) big-endian StrongARM* Linux port. – 60 day

  22. Slide 22: Development Environments for VxWorks and Linux

    Development Environments for VxWorks and Linux Volume I (VxWorks) Volume II (Linux) Design Model/Libraries StrongARM* Core Library ACE model and libraries Tools Provided Wind River Systems* GNU gcc 2.95.2, gdb 4.18 Tornado 2.0.1 (trial version) cygwin env. for NT NCL, IDL Compilers Embedded Linux ID

  23. Slide 23: IXP1200 Development Station

    IXP1200 Development Station Embedded VxWorks or Linux (sample configuration) Microengine Toolchain IXM1200 Network 500Mhz Pentium III Developer’s Workbench 2.0 Processor Base System Controller (Installed from Vol. I or II CD) Card (SBC) StrongARM VxWorks Or Linux Toolchain Wind River Tornado 2.01 PC

  24. Slide 24: Agenda

    Agenda  Overview  What is a Network Processor?  Overview of the IXP1200 Family  Introduction to "IXP2400"  Introduction to "IXP2800"  Development Tools  Example Intel® IXA Applications  Summary Page 24

  25. Slide 25: Intel IXA – The Next Generation

    Intel® IXA – The Next Generation Customer Applications  Intel® IXA characteristics: Enables software Intel® IXA portability framework portability – Definable: Intel® IXA is Intel’s packet processing architecture Intel® IXA Network Processor focused on our network Enables low power, high processors

  26. Slide 26: Intel Network Processor Roadmap

    Intel Network Processor Roadmap Bridgton (full Duplex 192) OC-192 IXP2800 Tiburon  Q2’03 (integration) OC-48 IXP2400 Jonesport  Q4’02 (cost reduction) IXP1200 OC-12 IXP1200 IXP1240 IXP1240 C-0 step IXP1250 IXP1250 Q1’02 Q1’01 Q2’01 Q3’01 Q4’01 Q1’02 Q2’02 2H’02 1H’03 2H’03 Center of Products are

  27. Slide 27: IXP2400 External Features

    IXP2400 External Features External Interfaces Host PCI 64-bit / 66 MHz  Interface supports UTOPIA 1/2/3, CPU (Optional) SPI-3 (POS-PL3), and CSIX.  Four independent, configurable, 8- QDR SRAM bit channels with the ability to Classification 20 Gbps aggregate channels for wider Accelerator IXP2400 3

  28. Slide 28: IXP2400 Internal Architecture

    IXP2400 Internal Architecture 72 Stripe/byte align MEv2 MEv2 DDRAM 1 2 Rbuf S 32b 32b 64 @ 128B P I 3 or MEv2 MEv2 C 4 3 S G I PCI XScale A Tbuf X 32b 64b Core S 64 @ 128B (64b) K 32K IC 66 MHz E 32K DC T MEv2 MEv2 Hash 5 6 64/48/128 Scratch 16KB QDR QDR CSRs MEv2 MEv2 -Fast_wr -UART SRAM SRAM 8 7 -

  29. Slide 29: IXP2400 Internal Features

    IXP2400 Internal Features Internal Product Capabilities  Eight next generation Microengines (MEv2) operating at 600MHz with significant architecture enhancements such as: – Automated packet scheduling and handling to free MEv2 cycles for packet processing – Local data store enables higher performan

  30. Slide 30: Micro-engine version 2 (MEv2)

    Micro-engine version 2 (MEv2)  New Features and Instructions  Enhanced Event signaling & Thread-control  More execution resources Page 30

  31. Slide 31: Microengine V2

    Microengine V2 From Next Neighbor D-Push Bus S-Push Bus Local 128 128 128 Next 128 D 128 S Memory GPR GPR Neighbor Xfer In Xfer In Control Store 4K LM Addr 1 2 per Instructions LM Addr 0 CTX P-Random # A_Operand B_Operand CRC Unit CAM Multiply Execution CRC remain Find first bit Data path Local Add,

  32. Slide 32: MEv2 new features & instructions

    MEv2 new features & instructions  Local Memory – Facilitates development and efficient execution of structured applications – Refer to them via index registers similar to GPR’s – Holds 640 long-words – Access latency is like register’s  Next Neighbor registers – Facilitates efficient software pipe

  33. Slide 33: MEv2 new features & instructions

    MEv2 new features & instructions  CAM (Content Addressable Memory) – Improves usage of multiple threads on same data – Result can be used to dispatch to the proper code. Lock can flag in-flight or changing data. – Performs parallel look-up on 16 entries of 32-bit value. Reports miss, hit, or locked

  34. Slide 34: MEv2 Event signaling & Thread-control

    MEv2 Event signaling & Thread-control  Provides 8 threads Vs 4 in IXP1200 – Can configure as 8, 4 threads with entire MEv2 resources (GPR, memory, Txfr Reg, etc).  Each thread has its own program counter, registers, signal & wakeup events  Each thread uses up to 15 event signals: – DRAM & SRAM tr

  35. Slide 35: MEv2 Execution Resources

    MEv2 Execution Resources  More registers on each ME – 256 General Purpose Registers Vs 128 in IXP1200 – 512 Transfer Registers Vs 128 in IXP1200 – ME resources divided among user defined # of threads  4K-instruction Control Store Vs 2K in IXP1200 Page 35

  36. Slide 36: MEv1 Versus MEv2

    MEv1 Versus MEv2 MEv1 MEv2 Configurable to Threads / ME 4 4, 8 General Purpose Registers 128 256 Transfer Registers 128 512 Next Neighbor Registers None 128 Local Memory None 640 Long Words Control Store 2K 4K Branch Boundary 1K None CAM None 16 32-bit entries Pseudo Random Number None Yes Gen CRC_1

  37. Slide 37: IXP2400 Target Applications

    IXP2400 Target Applications IXP2400 will provide IXP 1200 customers a performance upgrade for OC-12 applications and enable platforms up to OC-48.  WAN Edge/Access Aggregation • Includes IP Service Switches, Multiservice Switches, DSLAM, Cable Head End  Wireless Infrastructure • BSC/RNC, xGSN, PDS

  38. Slide 38: Agenda

    Agenda  Overview  What is a Network Processor?  Overview of the IXP1200 Family  Introduction to "IXP2400"  Introduction to "IXP2800"  Development Tools  Example Intel® IXA Applications  Summary Page 38

  39. Slide 39: Intel Network Processor Roadmap

    Intel Network Processor Roadmap Bridgton (full Duplex 192) OC-192 IXP2800 Tiburon  Q2’03 (integration) OC-48 IXP2400 Jonesport  Q4’02 (cost reduction) IXP1200 OC-12 IXP1200 IXP1240 IXP1240 C-0 step IXP1250 IXP1250 Q1’02 Q1’01 Q2’01 Q3’01 Q4’01 Q1’02 Q2’02 2H’02 1H’03 2H’03 Center of Products are

  40. Slide 40: What is IXP2800?

    What is IXP2800?  Single chip OC-192 / 10 GbE network processor that combines Layer 3 / 4 forwarding and traffic management functions at wire rate – Fully software programmable store and forward architecture – Industry standards interfaces to memory subsystems, media and switch fabrics – Does not r

  41. Slide 41: IXP2800 – highlights

    IXP2800 – highlights  2nd generation network processor  1.4 GHz operation delivers 20+ Giga-operations per second  10 Gbs full duplex media interface  50 Gbs packet memory bandwidth  30 Million packets per second L4 forwarding  60 Million Enqueue/Dequeue operations/sec  Advanced HW support fo

  42. Slide 42: IXP2800 features

    IXP2800 features  (16) Multi-threaded microengines – 8 threads per engine – 4 K word control stores – 1.4 GHz operating frequency  XScale Core – 700 MHz operating frequency – 32 Kbytes instruction cache / 32 Kbytes data cache  Media / Switch Fabric Interface – 2 x 16 bit LVDS Transmit & Receive –

  43. Slide 43: IXP2800 features con't

    IXP2800 features con’t  PCI Interface – 64 bit / 66 MHz interface for control  QDR Interface (with parity) – (4) 36 bit SRAM channels (QDR or coprocessor) – Network Processor Forum proposed coprocessor Standard Interface  Rambus DRAM Interface (w/ECC) – (3) Independent direct Rambus DRAM interfac

  44. Slide 44: IXP2800

    72 72 72 Stripe/byte align IXP2800 RDRAM RDRAM RDRAM MEv2 MEv2 MEv2 MEv2 1 2 3 1 2 3 4 Rbuf S 16b 16b 64 @ 128B P I MEv2 MEv2 MEv2 MEv2 4 8 7 6 5 or G PCI XScale A C S 64b 64b Core S I (64b) 32K IC K Tbuf X 16b 66 MHz E 64 @ 128B 32K DC T MEv2 MEv2 MEv2 MEv2 9 10 11 12 Hash 64/48/128 Scratch QDR QDR

  45. Slide 45: Microengine version 2

    Microengine version 2 From Next Neighbor D-Push S-Push Bus Bus Local 128 128 128 Next 128 D 128 S Memory GPR GPR Neighbor Xfer In Xfer In 640 words Control Store 4K LM Addr 1 2 per B_op A_op Instructions LM Addr 0 CTX Prev B Prev A P-Random # A_Operand B_Operand CRC Unit Multiply Status and TAGs 32-

  46. Slide 46: IXP2800 ecosystem

    IXP2800 ecosystem  QDR suppliers - 18/36 Mb ( http://www.qdrsram.com ) – Micron / MT54V512H18A – IDT / IDT71T6280H – Cypress / CY7C1302V25 – Samsung & NEC  RDRAM suppliers - 288/576 Mb – Samsung / 750948-001 – Elpida (NEC & Hitachi) – Toshiba  QDR look aside coprocessor (see Intel for vendor cont

  47. Slide 47: Intel complementary technology

    Intel complementary technology  SPI-4 Peripherals – Calypso (1x10 Gb/sec Ethernet MAC) samples Q102 from Intel OPG – Ben Nevis (10x1Gb/sec Ethernet MAC) samples Q102 from Intel NCD – Calypso (OC-192 Framer, POS/ATM/Ethernet/HDLC) from Intel OPG – Bachelor (4xOC-48 & 16xOC-12 POS Framer) Intel OPG 

  48. Slide 48: IXP2800 target applications

    IXP2800 target applications  Core Applications  Edge / Access Access  Enterprise – Core routers – Metropolitan Area – Switches/routers Network – Data center / SAN Switches/routers – Edge Routers – Multi-service Switches – Aggregation – Security – Content Aware L4-L7 – Wireless Infrastructure Swit

  49. Slide 49: Agenda

    Agenda  Overview  What is a Network Processor?  Overview of the IXP1200 Family  Introduction to "IXP2400"  Introduction to "IXP2800"  Development Tools  Example Intel® IXA Applications  Summary Page 49

  50. Slide 50: Intel Development Platform Roadmap

    Intel Development Platform Roadmap Bridgton (full Duplex 192) OC-192 Deer Island Dev. Platform Q2’03 IXP2800 Q2’03 Tiburon  Angel Island (integration) Dev. Platform Q1’03 OC-48 IXP12EB IXDP1200 Development IXP2400 Jonesport Evaluation Kit Platform  Q4’02 (cost reduction) IXP1200 OC-12 IXP1240 IXP1

  51. Slide 51: Table of Baseboards and Media Cards

    Table of Baseboards and Media Cards Baseboards Media Cards Battery Drew – OC-48 PoS Media Battery Wallace – Quad OC-12 PoS Media KENT ISLAND Point Lone – Quad Gigabit Ethernet Media (Dual IXP2400 NPU) Battery Ledyard –PoS /ATM OC-48 H/W SAR Bird Island - Switch Fabric Loopback Marin Island – QDR Mod

  52. Slide 52: Development Platform Components

    Development Platform Components Modular Chassis Baseboard 20mm Media Card 366 mm (9U) serial serial LED Stacks RJ RJ CLK O conn conn BUF S 45 45 5V C 2.5V 2.5V Transp 232 drvr 232 drvr onder 3.3V Light Logic I/O LVDS TXN13303 38-PIN NPU cap cap Transp NIC1 NIC2 onder & Calypso Mictor 38-PIN cap cap

  53. Slide 53: IXA Software Development Kits (SDK) Roadmap

    IXA Software Development Kits (SDK) Roadmap IXP2800 IXA SDK Pt. Reyes 3.0 IXA SDK (IXP2400/ 3.1 IXP2800) IXP2400 SDK 2.01 Calaveras (patch IXA SDK 2.1 IXP1200 IXA SDK IXA SDK release) IXP1240 1.3 2.0 IXP1250 Q1’01 Q2’01 Q3’01 Q4’01 Q1’02 Q2’02 Q3’02 Q4’02 Q1’03 End annc’d (PDA’d) Shipping Developmen

  54. Slide 54: Simulation / Development Environment

    Simulation / Development Environment Workbench GUI Editor, Debugger, … MEv2 Development XScale Development Serial/Ethernet/PCI/JTAG Assembler connection Assembler Linker Linker uC Compiler C/C++ Compiler Object Std Debug Object Std Debug MEv2 Simulation Transactor Hardware Debug Environment Foreign

  55. Slide 55: XScale Development Tools

    XScale Development Tools  Supplied by 3rd parties  Leveraging existing tools and vendors widely accepted in the industry  Optimized for XScale Microarchitecture  Cross-development tools for VxWorks – Windows hosted Tornado toolchain from WindRiver – Graphical IDE  Cross-development tools for em

  56. Slide 56: Production Building Blocks

    Production Building Blocks  Ipv4 L3 Forwarding (RFC1812 compliant)  Queue Manager  Transmit Scheduler  Interfaces (Transmit and Receive) – Vallejo Quad GbE – Ben Nevis 10x1 GbE – Calypso OC-192 POS/Ethernet – IXF6048 OC48 POS – IXF6048 Quad OC12 ATM  Control Plane – TCP/IP Stack interface – Rou

  57. Slide 57: Applications

    Applications  Demonstrate how to use production building blocks  Applications will be available for both IXP2800 and IXP2400 – Ethernet – Packet over SONET – ATM  Each application includes the following functions – Packet assembly – Flow and multi-field classification – IP verify and forwarding –

  58. Slide 58: Agenda

    Agenda  Overview  What is a Network Processor?  Overview of the IXP1200 Family  Introduction to "IXP2400"  Introduction to "IXP2800"  Development Tools  Example Intel® IXA Applications  Summary Page 58

  59. Slide 59: IXP2400 Full-Duplex OC-48 System Implementation

    IXP2400 Full-Duplex OC-48 System Implementation S D DDR SDRAM QDR SRAM Q Q R Packet Queues & D D A Memory Tables R R M T Host CPU C Classification A Accelerator (IOP or iA) IXP2400 M Receive Processor OC-48 OC48 Switch IXF6048 Fabric Framer Gasket OC48 OC48 1x OC-48 or IXP2400 T 4x OC-12 C Classific

  60. Slide 60: IXP2400 Edge Multi-Service Switch - OC-48 WAN/LAN Solutions

    IXP2400 Edge Multi-Service Switch - OC-48 WAN/LAN Solutions Utopia3 1 Gig LAN or Server Farm Phy Interface IXP2400 SPI-3 (Utopia3 Packet) SPI-3 (Utopia3 Packet) Amazon Oahu Vallejo IXF6048 Quad 4 x 1G OC-48c Gig Ethernet ATM & POS Phy MAC Framer WAN Backbone Optical 1 Gig (ATM, SONET) Ring LAN Backb

  61. Slide 61: IXP2400 OC12+/GbE 3G RNC Line Card

    IXP2400 OC12+/GbE 3G RNC Line Card PCI Bus Host CPU (IOP or iA) Utopia 3 (2 X 8) Phy Interface SPI-3 (2 X 8) IXP2400 Amazon Oahu Vallejo IXF6048 Quad 4 x 1G Quad Quad OC12 Gig Ethernet OC-12 POS/ATM Phy MAC PHY Framer No Connect/No Use Page 61

  62. Slide 62: IXP2400 Edge / Access Networks - Multiple Line Card Solutions

    IXP2400 Edge / Access Networks - Multiple Line Card Solutions IXP2400 Server Farm 1 Gig to 4x Gig Future Phy IXP2400 Slot 1 Txcvr WAN Access IXP2400 16x OC-3 CSIX Switch Txcvr Centaur Fabric (3rd Party) IXP2400 Txcvr 80 Gig to Slot 2 1+ Terabit Switch Fabric WAN Backbone IXP2400 OC-48 Txcvr IXF6048

  63. Slide 63: IXP2800 10Gbps SONET line card

    IXP2800 10Gbps SONET line card Ingress Processor D D D RDR SAR’ing QDR SRAM Q Q Q Q R R R Control Plane Queues & D D D D A A A Packet Processor Classification M M M Memory Metering Tables R R R R Policing PCI 64/66 Initial Congestion IXP2800 Management Ingress Processor Fabric Interface Calypso CDR,

  64. Slide 64: IXP2800 10Port 1Gbps Ethernet line card

    IXP2800 10Port 1Gbps Ethernet line card Ingress Processor D D D RDR SAR’ing QDR SRAM Q Q Q Q R R R Control Plane Queues & D D D D A A A Packet Processor Classification M M M Memory Metering Tables R R R R Policing PCI 64/66 Initial Congestion IXP2800 Management Ingress Processor Fabric Interface Ben

  65. Slide 65: IXP2800 10Gbs Ethernet to SONET card

    IXP2800 10Gbs Ethernet to SONET card D D D RDR QDR SRAM Q Q Q Q R R R Control Plane Queues & D D D D A A A Packet Processor M M M Memory Tables R R R R PCI 64/66 IXP2800 Ben Nevis Ingress Processor Calypso Server 10Gbs Metro 10Gbs or 10GbE SPI SPI OC-192 Flow Ctl Or Disk 10x1Gb I/F I/F 4xOC48 Farms

  66. Slide 66: IXP2800 system w/ SPI gasket

    IXP2800 system w/ SPI gasket D D D QDR SRAM Q Q Q Q R R R RDR Control Plane Queues & D D D D A A A Packet Processor M M M Tables R R R R Memory PCI 64/66 IXP2800 Ingress Processor 10Gbs 10Gbs Dual Dual Utopia3 Utopia3 SPI4 or x or 2 CSIX U3 CSIX SPI SPI4 x 2 2 U3 U3 SPI gasket Page 66

  67. Slide 67: IXP2800 system w/ chaining

    IXP2800 system w/ chaining  Glueless interface between IXP2800 devices Control Plane Processor PCI 64/66 10Gbs IXP2800 10Gbs IXP2800 10Gbs IXP2800 10Gbs SPI-4 Processor SPI-4 Processor SPI-4 Processor SPI-4 Q Q Q Q D D D Q Q Q Q D D D Q Q Q Q D D D D D D D R R R D D D D R R R D D D D R R R R R R R

  68. Slide 68: Agenda

    Agenda  Overview  What is a Network Processor?  Overview of the IXP1200 Family  Introduction to "IXP2400"  Introduction to "IXP2800"  Development Tools  Example Intel® IXA Applications  Summary Page 68

  69. Slide 69: IXP Family Feature Summary

    IXP Family Feature Summary IXP1200 IXP1240 IXP1250 IXP2400 IXP2800 Performance Full Dup Full Dup Full Dup OC-12 ½ Duplex OC-48 ½ Duplex Rating OC-12 OC-12 OC-192 Microengines 6 x v1 6 x v1 6 x v1 8 x v2 16 x v2 Control Store 1K 2K 2K 4K 4K Clock Rate 200 MHz 232 MHz 232 MHz 600 MHz 1400 MHz Media In

  70. Slide 70: Summary / Thank You

    Summary  Intel® IXA is not a point product – it is a family of silicon and software with a supporting ecosystem  The depth and breadth of Intel® IXA is unmatched in the industry – and this applies to silicon, software, tools, and the ecosystem  Intel® IXA addresses real applications with highly c

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