Monolithic Power Systems, Inc. · NASDAQ:MPWR
Monolithic Power Systems — Technical Presentation (August 2023)
17 slides from Monolithic Power Systems's technical presentation, August 2023
Slide 1: Myth-busting for commonly used EMI reduction techniques in power converter design
Myth-busting for commonly used EMI reduction techniques in power converter design Zheng Luo – MPS Francesc Estragués - MPS IS20.4 1 of 18
Slide 2: Introduction
Introduction In many seminars we are presented with a suite of techniques to improve the Electro-Magnetic Compatibility (EMC) of our designs. These techniques don’t often come with accurate A to B comparisons to evaluate if they are true, or “quantify” the impact of a particular implementation. EMC
Slide 3: Methodology
Methodology In order to accurately study the effect of each individual design technique we have designed a set of PCBs that share a similar layout but each featuring a specific change. Standard Reference PCB Layout variants 3 of 18
Slide 4: Methodology
Methodology All PCB variants share the same schematics, in some cases the components were populated in different positions for the comparison. MPQ43XX 4 of 18
Slide 5: Methodology
Methodology The input harness follows CISPR25 standard. The output resistor is connected with short cables to the PCB. All test procedures follow CISPR25. PCB test setup 5 of 18
Slide 6: Case 1: Symmetrical Input Capacitors
Case 1: Symmetrical Input Capacitors What is the myth about? When placing the input capacitors symmetrically, creating 2 opposing current loops, the magnetic fields created by the dI/dt cancel each other as they have opposite directions. 6 of 18
Slide 7: Case 1: Symmetrical Input Capacitors - How it was tested
Case 1: Symmetrical Input Capacitors How it was tested Symmetric Cin Symmetric Cin Non-symmetric Non-symmetric w/o small cap Cin w/ small cap Cin w/o small cap TB6 TB6’ TB3 TB3’ 7 of 18
Slide 8: Case 1: Symmetrical Input Capacitors - Test results
Case 1: Symmetrical Input Capacitors Test results In the FM band Symmetric Cin is always better. Having the 100nF capacitor is always better. CISPR25 Class 5: CE Average measurements 2dB TB6: Symmetric Cin with 3dB 100nF 2dB TB6’: Symmetric Cin removing 100nF TB3: Asymmetric Cin with 100nF TB3’: Asy
Slide 9: Case 1: Symmetrical Input Capacitors - Test results
Case 1: Symmetrical Input Capacitors Test results In 1 and 3 the symmetric Cin is ~8dB better. In 2 the symmetric Cin is ~8dB worse. In 4 it is ~3dB worse. The 100nF capacitor is always an improvement. CISPR25 Class 5: RE Log Average measurements (Vertical) TB6: Symmetric Cin with 100nF TB6’: Symmet
Slide 10: Case 1: Symmetrical Input Capacitors - Myth-busting
Case 1: Symmetrical Input Capacitors Myth-busting The symmetrical input capacitors help improve the EMI in the critical FM band for the Conducted Emissions test. The 100nF capacitors are helpful in almost all frequencies. In the Radiated Emissions test, the symmetrical CIN improve the emissions in m
Slide 11: Case 2: Ground plane splitting
Case 2: Ground plane splitting What is the myth about? Return currents in the GND plane are mostly concentrated next to their source conductor, but part of them is spread over a wider surface of the plane. These larger current loops form a magnetic antenna and will radiate. By cutting the GND portio
Slide 12: Case 2: Ground plane splitting - How it was tested
Case 2: Ground plane splitting How it was tested Top layer PGND cut Top layer PGND cut PGND cut GND cut GND cut No cut on top layer Internal layer GND cut Solid internal layer GND Solid internal layer GND Solid internal layer GND TB6 TB11 TB12 TB13 12 of 18
Slide 13: Case 2: Ground plane splitting - Test results
Case 2: Ground plane splitting Test results There is not too much difference CISPR25 Class 5: CE Average measurements TB6: All GND cuts TB11: Removing Internal GND cut TB12: Removing Internal and Top GND cut TB13: Removing all cuts 13 of 18
Slide 14: Case 2: Ground plane splitting - Test results
Case 2: Ground plane splitting Test results Cutting the GND in several locations makes things worse. The best case is when making a local cut to the PGND. CISPR25 Class 5: RE Log Average measurements (Vertical) TB6: All GND cuts TB11: Removing Internal GND cut TB12: Removing Internal and Top GND cut
Slide 15: Case 2: Ground plane splitting - Mythbusting
Case 2: Ground plane splitting Mythbusting Splitting the GND plane does not have a significant impact on EMI (<1 dBµV/m). Cutting the GND plane in multiple areas degrades the GND impedance, making the board worse. S T E D B U 15 of 18
Slide 16: Conclusions
Conclusions • Many EMC recommendations given in seminars are not valid across all designs. There are several variables at play (PCB size, load type, harnesses…). • The way to ensure if a design is going in the right direction is through testing or simulating in the early stages of development. • Sta
Slide 17: Q&A
Q&A 17 of 18
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