Asml Holding Nv · EURONEXT:ASML
Asml Holding Nv — Deutsche Bank 2007 Technology Conference London
30 slides from Asml Holding Nv's conference presentation, Oct 4, 2007
Slide 1: Deutsche Bank 2007 Technology Conference London
Deutsche Bank 2007 Technology Conference London Franki D'Hoore Director Investor Relations 14 September, 2007
Slide 2: Safe Harbor
Safe Harbor "Safe Harbor" Statement under the U.S. Private Securities Litigation Reform Act of 1995: the matters discussed in this document may include forward-looking statements that are subject to risks and uncertainties including, but not limited to: economic conditions, product demand and semico
Slide 3: ASML overview - The world's leading provider of lithography systems
ASML overview - The world's leading provider of lithography systems for the semiconductor industry Established: 1984 Headquarters: Veldhoven, the Netherlands Market cap ~ €10 B Employees ~ 6,200 Customers: Serving 17 of the top 20 semi mfg. Equity Listing: Nasdaq and Euronext Key facts Key financial
Slide 4: Industry growth drives lithography tool consumption
Sources: ASML MCC, VLSI Research, iSuppli, SIA Industry growth drives Lithography tool consumption - NAND Flash fastest growing DRAM LOGIC NAND NOR ANALOG MICRO Other 0 10 20 30 40 50 60 0 5 10 15 20 25 30 CAGR Exposure Area 06-09 [%] Exposure area 2006 [SI*10^9] Segment size: 20 Bio. US$
Slide 5: NAND Flash customer roadmaps drive lithography tool development
NAND Flash Customer Roadmaps drive Lithograph tool development Jan-00 Jan-02 Jan-04 Jan-06 Jan-08 Jan-10 Jan-12 Half Pitch (nm) 200 100 80 60 40 Logic DRAM Half Pitch status : Logic = 65~90nm DRAM = 60~80nm NAND = 55~65nm
Slide 6: ASML Lithography Roadmap 300mm
ASML Lithography Roadmap 300mm
Slide 7: ASML TWINSCAN Product Specifications Continuous Improvement
ASML TWINSCAN? Product Specifications Continuous Improvement
Slide 8: ASML roadmap enables shrink for Logic, DRAM, and NAND flash
ASML roadmap enables shrink for Logic, DRAM, and NAND flash at time required Source: Various customers, dates determine production start/qualification 10 12 200 100 80 60 40 11 07 09 08 04 06 05 01 03 02 00 Resolution/half pitch "Shrink" [nm] Year ASML Product Introduction XT:1400 XT:1700i AT:1200 A
Slide 9: Technology in Time helps grow market share
84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 Region 1 0 1 2.5 8.5 7.5 10.5 11.5 10.5 21 21 19 19.5 25.5 31 36 41 41 30 54 45 53 56.5 63 Technology in Time helps grow market share Technology in Time helps grow market share Technology in Time helps grow market share Total marke
Slide 10: Immersion leadership continues
KrF ArF dry ArF wet I line East 15 37 42 6 West North Immersion - Leadership continues Over 50 systems shipped to date to all applications and geographies in the world 25 immersion machines in backlog valued at € 728 M Received repeat orders from major Japanese customers including multiple XT:1900i
Slide 11: First TWINSCAN XT:1900i shipped on schedule early July
First TWINSCAN XT:1900i shipped on schedule early July First tool in the world capable of printing features below 40 nm in volume production in volume production in volume production
Slide 12: Million wafers processed on ASML immersion systems
Over 2 Million wafers processed on ASML immersion systems with steep production ramp since April 2007 systems with steep production ramp since April 2007 systems with steep production ramp since April 2007 Wafers exposed on ASML immersion equipment
Slide 13: The layout designers draw is not quite what gets printed
180nm 130nm 90nm 65nm The layout designers draw, is not quite what gets printed by scanners
Slide 14: Why is this happening?
Why is this happening? Because the litho process is not an error-free transfer function Mask-writing Wafer exposure Resist development Etch H ^ 1
Slide 15: What can we do about it?
What can we do about it? Software compensation for the distortion H .... .... .... ~1/H
Slide 16: Mask with correction, RET/OPC
Mask (with correction, or "RET/OPC") Silicon Image w/o correction Design Layout Mask (no correction) Silicon Image with RET/OPC In practice...
Slide 17: What does Brion do?
What does Brion do? Mask-writing Wafer exposure Resist development Etch H ^ 1 Accurate mathematical model of "H" Designers drawing Simulated wafer, before you print anything
Slide 18: With an accurate mathematical model of H, we can do two things
With an accurate mathematical model of H, we can do two things: Compensate on design Compensate on scanner i.e. Approximate 1/H i.e. Find H' so distortion is less and/or easier to compensate for Brion's Tachyon OPC+ product line Scanner tuning
Slide 19: Fine tuning system settings through an accurate model
Through accurate model, we can fine tune many system settings for optimum exposure of each device pattern, reticle & wafer Lens Illuminator Sigma Pupicom PSEs DOEs Dose Unicom Etc. Stages Laser Bandwidth NA Manipulators Focus Tilt X Tilt Y Reticle height Synchronization
Slide 20: Synergies of owning the scanner and the litho model
Synergies of owning the scanner and the litho model for scanner-tuning System setting ranges : NA range Illumination option/ranges standard & custom DoseMapper correction range etc. Actual system data Lens heating characteristics Aberration data Stray light Laser bandwidth etc. Wafer metrology & exp
Slide 21: The holy-grail of optimisation: today, only ASML can do this
The holy-grail of optimisation: today, only ASML can do this Optimized Scanner (e.g. Illumination) Non - Optimized Mask Top-down photoresist Optimize both the scanner and the mask, together, as a unified optimization problem
Slide 22: With Brion, ASML now can... (1/2)
With Brion, ASML now can... (1/2) Leverage a whole new dimension of possibilities for optimizing imaging performance (mask optimization, RET/OPC) as an integral part of its solution package Use an accurate model of the lithography process to tune the dozens of scanner knobs available so to further o
Slide 23: With Brion, ASML now can... (2/2)
With Brion, ASML now can... (2/2) Further secure the ArF roadmap until EUV is ready Prevent value-migration to EDA by capturing software solutions to printability Penetrate a new and growing market at the interface with EDA, capturing new value streams and enabling growth beyond "hardware"
Slide 24: Lithography system costs will continue to rise
1 10 100 1985 1990 1995 2000 2005 2010 Year Lithography System costs will continue to rise Relative List Price i-line 300mm 200mm 150mm KrF ArF ArFi EUV? Wafer Size Wavelength Stepper Platform Step & Scan Dual Stage 0.4 0.5 0.6 0.7 0.8 0.93 1.2 1.35 Aperture
Slide 25: Average Selling Price (ASP) grows
Average Selling Price (ASP) grows 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 3.59 4.38 5.4 5.9 6.8 8.92 9.46 9.28 13.54 14.01 MSGraph.Chart.8 MSGraph.Chart.8 ASML ASP new systems KrF & Step & Scan 300mm & ArF 300mm & ArF ArF volume & ArFi
Slide 26: Are lithography systems becoming unaffordable?
Are lithography systems becoming unaffordable? 1 10 100 1,000 10,000 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 150mm 200mm 300mm Relative price increase = 40% / generation Relative productivity increase (mm2/hour) = 30% / generation Relative shrink increase (pixels/field) = 100% /
Slide 27: Lithography affordability for future shrink
Lithography Affordability for Future Shrink Relative Performance 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.0 AT:1150C XT:1400E XT:1900i NEXTi EUVL 90nm 65nm 40nm 28* 22 2003 2005 2007 2009 2011 4GB 8GB 16GB 32GB 64GB Relative System Cost Relative System WPH Relative Cost / Function / Hour Model Resoluti
Slide 28: ASML Competitive Advantage
ASML Competitive Advantage 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2004 2005 2006 2007 2008 ASML ArF Competition ArF ASML ArFi Competition ArFi Pixels per Hour per Million Euro
Slide 29: Summary
Summary Shrinking design rules have been the economical driver of the IC industry. Lithography remains the key enabler Providing the right product at the right time allows market share gains for ASML Shrinking design rules require increasingly more sophisticated lithography systems resulting in a st
Slide 30: ASML Commitment
G “ee ASML Commitment
Asml Holding — Deutsche Bank 2007 Technology Conference London on 6ix