Synopsys, Inc. · NASDAQ:SNPS
Synopsys — Technical Presentation (June 2009)
31 slides from Synopsys's technical presentation, Jun 25, 2009
Slide 1: In-Design Rail Analysis for Faster Design Closure
IC Compiler 2009 Webinar Series In-Design Rail Analysis for Faster Design Closure IC Compiler and PrimeRail Tom Chau CAE Group Director June 25th, 2009 ©Synopsys2009 1 IC Compiler 2009 Webinar Series
Slide 2: Welcome!
Welcome! IC Compiler 2009 Webinar Series Congestion • Highlighting key technologies for Minimization speeding design closure • Previous topics: – Signoff-driven closure In-Design Physical IC Signoff- Driven – In-Design physical verification Verification Compiler Closure – Placement-congestion minimi
Slide 3: Welcome! Presenters Introduction
Welcome! Presenters Introduction Tom Chau CAE Group Director, Implementation Group Dr. Henry Sheng R&D Group Director, Design Closure in IC Compiler ©Synopsys2009 3 IC Compiler 2009 Webinar Series
Slide 4: Agenda
Agenda • Emerging Challenges • PrimeRail and IC Compiler • Traditional Approach to Power Network Closure • IC Compiler In-Design Rail Analysis with PrimeRail • Summary ©Synopsys2009 4 IC Compiler 2009 Webinar Series
Slide 5: Agenda
Agenda • Emerging Challenges • PrimeRail and IC Compiler • Traditional Approach to Power Network Closure • IC Compiler In-Design Rail Analysis with PrimeRail • Summary ©Synopsys2009 5 IC Compiler 2009 Webinar Series
Slide 6: Design Challenges Are On The Rise
Design Challenges Are On The Rise Lower Supply Voltages Less Margin 1.50 1.5V Supply 150 mV Margin 1.40 1.30 1.20 100 mV 1.10 Margin 1.00 1.0V Supply 0.90 2003 2005 2007 2009 2011 Chip Failure Source: ITRS 2008 Majority of Tape-outs Late Short Time-to-Market “Late stage ECO” “Meeting design is the r
Slide 7: Emerging Challenges Require A New Approach
Emerging Challenges Require A New Approach What’s Needed Tight integration Short Time-to-Market with implementation for faster design closure Early power network Majority of Tape-outs Late problem detection and fixing guidance for IC designers Decrease Supply Voltage Accuracy and predictability and
Slide 8: The Biggest Emerging Need
The Biggest Emerging Need Tightly Integrated Physical Design & Rail Analysis Implement-then-Verify In-Design Rail Analysis Power Network Design Power Network Design with In-Design Rail Analysis Translate Power Network Verification Power Network Verification ©Synopsys2009 8 IC Compiler 2009 Webinar S
Slide 9: Agenda
Agenda • Emerging Challenges • PrimeRail and IC Compiler • Traditional Approach to Power Network Closure • IC Compiler In-Design Rail Analysis with PrimeRail • Summary ©Synopsys2009 9 IC Compiler 2009 Webinar Series
Slide 10: IC Compiler: Accelerate Power Network Design
IC Compiler In-Design Rail Analysis Accelerate Power Network Design • Advanced rail analysis within P&R IC Compiler • Find and fix issues PrimeRail during physical implementation Milkyway • Embedded trusted PrimeRail technology ©Synopsys2009 10 IC Compiler 2009 Webinar Series
Slide 11: Continuous Innovation in Physical Design
Continuous Innovation in Physical Design In-Design Rail Analysis In-Design Verification 10X faster Routing Z-Route 2X Faster Flow Netlist - GDSII Incremental Design Rule Checking Concurrent Hierarchical Design Innovation in Physical Design ©Synopsys2009 11 IC Compiler 2009 Webinar Series
Slide 12: Agenda
Agenda • Emerging Challenges • PrimeRail and IC Compiler • Traditional Approach to Power Network Closure • IC Compiler In-Design Rail Analysis with PrimeRail • Summary ©Synopsys2009 12 IC Compiler 2009 Webinar Series
Slide 13: Traditional Power Network Closure
Traditional Power Network Closure Implement-Then-Verify Leads to Flow Spiral Rail Analysis Point Tool Iterative Loop Place & LEF / DEF Route Versions Compatible ?? Adds Risk and Time to Tape-out Schedule ©Synopsys2009 13 IC Compiler 2009 Webinar Series
Slide 14: Problems with Traditional Approach
Problems with Traditional Approach Risk Late Stage Surprises TIME P&R Rail Tool Tool Different Databases and Views LEF DEF P&R Rail DB DB P&R Designers IC Rail Design Analysis not Focused on Rail Analysis ©Synopsys2009 14 IC Compiler 2009 Webinar Series
Slide 15: Problems with Traditional Approach: Late Stage Surprises
Problems with Traditional Approach Late Stage Surprises • High cost of ping ponging between different tools • Design may have to be reworked • Implement-then-Verify concentrates risk at end of design stage • Leads to late tape-out Design Planning Power Design Placement Clock Design Routing Chip Fini
Slide 16: Problems with Traditional Approach: Different Databases and Views
Problems with Traditional Approach Different Databases and Views • Multiple databases requires data translations – Productivity lost to translation time • Resolving file format versions and compatibilities • Updating scripts continuously – Raises risk for translation errors • Multiple iterations req
Slide 17: Problems with Traditional Approach: Designers Not Focused on Rail Analysis
Problems with Traditional Approach Designers Not Focused on Rail Analysis • Power network verification & analysis is not designers’ main focus • No time in schedule to become an expert • Overdesigning is common for design closure Bolt-on Rail Analysis Solution ©Synopsys2009 17 IC Compiler 2009 Webin
Slide 18: Conclusion
Conclusion Traditional power network approach puts risk of tape-out schedule slip at the end of the project A flow enabling rail analysis within implementation is needed for faster closure ©Synopsys2009 18 IC Compiler 2009 Webinar Series
Slide 19: The Ideal Flow for Faster Power Network Closure
The Ideal Flow for Faster Power Network Closure Rail analysis during physical design Early detection, easy guidance and fixing Automated flow within the P&R tool Minimal learning curve for P&R engineer Silicon proven accuracy Predictability for faster turnaround time ©Synopsys2009 19 IC Compiler 200
Slide 20: Agenda
Agenda • Emerging Challenges • PrimeRail and IC Compiler • Traditional Approach to Power Network Closure • IC Compiler In-Design Rail Analysis with PrimeRail • Summary ©Synopsys2009 20 IC Compiler 2009 Webinar Series
Slide 21: Advanced Rail Analysis Within P&R
Advanced Rail Analysis Within P&R Single User Environment for Easy Adoption ©Synopsys2009 21 IC Compiler 2009 Webinar Series
Slide 22: Advanced Rail Analysis Within P&R: Resistivity Map
Advanced Rail Analysis Within P&R Viewing Rail Analysis Results In IC Compiler Resistivity Map ©Synopsys2009 22 IC Compiler 2009 Webinar Series
Slide 23: Advanced Rail Analysis Within P&R: Voltage Drop Map
Advanced Rail Analysis Within P&R Viewing Rail Analysis Results In IC Compiler Resistivity Map Voltage Drop Map ©Synopsys2009 23 IC Compiler 2009 Webinar Series
Slide 24: Advanced Rail Analysis Within P&R: Electromigration Map
Advanced Rail Analysis Within P&R Viewing Rail Analysis Results In IC Compiler Resistivity Map Voltage Drop Map Electromigration Map ©Synopsys2009 24 IC Compiler 2009 Webinar Series
Slide 25: Find & Fix Issues in Physical Design
Find & Fix Issues in Physical Design Early Detection and Fixing Guidance in IC Compiler Query by error types – Voltage Drop violations – Electromigration (EM) violations – Missing vias – Missing wire connections Browse individual error Display error details & fixing guidance Fix in IC Compiler ©Syno
Slide 26: Built on Trusted PrimeRail Technology
Built on Trusted PrimeRail Technology High Correlation with HSPICE and Silicon Within 10% of HSPICE Silicon Proven Dynamic Peak IR Drop 300 250 200 Recent Tape-outs using 150 PrimeRail Dynamic & Static 100 Analysis: 50 0 • 90nm LP test chip with 6 CPU cores HSPICE PrimeRail • 90nm TV chip • 65nm CPU
Slide 27: In-Design Rail Analysis Flow
In-Design Rail Analysis Flow Accelerate Power Network Design • Implement your power network – Power Network Synthesis (PNS) in IC Compiler – Manual or script-generated power network creation • Use IC Compiler In-Design rail analysis at every design phase for faster and more accurate design closure D
Slide 28: Common Database Leads to Predictable Success
In-Design Rail Analysis Flow Common Database Leads to Predictable Success • From IC Compiler In-Design Rail Analysis Solution – Cell/FrameView – Netlist IC Compiler – SDC Place and macro Route – UPF CCS PrimeRail HSIM Technology • To IC Compiler Milkyway – Error View – Rail View ©Synopsys2009 28 IC
Slide 29: Demo at DAC 2009 Preview: Fixing Electromigration Violations
Demo at DAC 2009 Preview – Fixing Electromigration (EM) Violations • In IC Compiler IC Compiler – Run In-Design Rail Run EM analysis Analysis – Fix EM issues based Fix EM issues on guidance from IC Compiler Error Run DRC/LVS Browser – Run In-Design DRC/LVS to make sure the updated power network is c
Slide 30: Agenda
Agenda • Emerging Challenges • PrimeRail and IC Compiler • Traditional Approach to Power Network Closure • IC Compiler In-Design Rail Analysis with PrimeRail • Summary ©Synopsys2009 30 IC Compiler 2009 Webinar Series
Slide 31: In-Design Rail Analysis: Faster Power Network Closure
In-Design Rail Analysis Faster Power Network Closure • Tight integration between rail IC Compiler analysis and physical design – enables early detection & fixing PrimeRail – eliminates late stage surprises – makes it easier to use for P&R Milkyway designers 0 Violations – eliminates costly translati