Asml Holding Nv · EURONEXT:ASML
Asml Holding Nv — Investor Day (November 2018)
28 slides from Asml Holding Nv's investor day presentation, Nov 9, 2018
Slide 1: EUV Products and Business Opportunity
Public EUV Products and Business Opportunity Christophe Fouquet Executive Vice President – Business Line EUV
Slide 2: ASML EUV Lithography product and business opportunity Key Messages
ASML EUV Lithography product and business opportunity Key Messages Slide 8 November ASML EUV lithography extends our Logic and DRAM customers roadmap by providing lithography resolution improvement, state of the art overlay performance and year on year cost reduction Our customers are preparing for
Slide 3: EUV – ASML Small Talk 2018
EUV – ASMLSMALLTALK2018 Veldhoven, November 8, 2018 Public Slide 3 8 November 2018 • EUV Lithography … extend our Logic and DRAM customer roadmap • Our customers …. are preparing to ramp EUV at 7nm Logic, 16nm DRAM • EUV industrialization and infrastructure … is ready to support 2019 ramp • EUV road
Slide 4: ASML EUV Lithography value for our customer
ASML EUV Lithography value for our customer 8 November Process simplification and improved device performance 15 to 50% cost reduction compared to multi-patterning schemes 3 to 6x cycle time reduction compared to critical multi-patterning layers Best in class overlay performance and focus performanc
Slide 5: EUV – ASML Small Talk 2018
EUV – ASMLSMALLTALK2018 Veldhoven, November 8, 2018 • EUV Lithography … extend our Logic and DRAM customer roadmap • Our customers …. are preparing to ramp EUV at 7nm Logic, 16nm DRAM • EUV industrialization and infrastructure … is ready to support 2019 ramp • EUV roadmap … combines 0.33NA extension
Slide 6: EUV ramp at our Logic customers has started
EUV ramp at our Logic customers has started with Public production in Logic and DRAM expected in 2019 Slide 6 8 November 2018 Cumulative exposed 3.2M EUV wafers posed 2.0M ex 1.1M ES Jung, EVP Foundry wafers Seoul October 18th, 2018 of # 0.6M The initial EUV production has started in Samsung’s S3 Fa
Slide 7: Our customers are not only talking about EUV
Our customers are not only talking about EUV Building significant capacity for EUV systems 8
Slide 8: EUV layer adoption increased for Logic
EUV layer adoption increased for Logic Expected EUV layer adoption DRAM Public Slide 8 8 November 2018 +50% next node +50% next node layers +30% realized EUV x3 opportunity of # 7nm Node 5nm Node 16nm Node 1A nm Node Logic adoption has increased by 30% for 7nm, 50% Final DRAM layer adoption for firs
Slide 9: EUV estimated demand per fab by market
EUV estimated demand per fab by market Range of layers and corresponding systems per fab1 Fab Capacity Market EUV layers EUV systems/fab (kwspm2) Logic 45 10 – 20 10 – 20 (7nm – 5nm) DRAM 100 1—6 2—10 (16nm -1Anm) Logic EUV capacity: 1 EUV layer requires 1 EUV system for every 45k wafer starts per m
Slide 10: EUV – ASML Small Talk 2018
EUV – ASMLSMALLTALK2018 Veldhoven, November 8, 2018 • EUV Lithography … extend our Logic and DRAM customer roadmap • Our customers …. are preparing to ramp EUV at 7nm Logic, 16nm DRAM • EUV industrialization and infrastructure … is ready to support 2019 ramp • EUV roadmap … combines 0.33NA extension
Slide 11: Customers are routinely running >1000 wafers per day
Customers are routinely running >1000 wafers per day, >2000 wafers per day demonstrated capability 8 Actual Customer Good Wafers Per Day (various conditions) Capability in ATP wafers (20mj/cm2), 100% utilization actual availability Wafers per day record of > 2200 day r pe Productivity Capability (WP
Slide 12: Availability performance has improved to support high volume manufacturing
Availability performance has improved to level supporting high volume manufacturing Slide 8 November Target Best in class systems availability demonstrated system 90% Last 6 months
Slide 13: Public Slide
Public Slide 13 8 November 2018
Slide 14: EUV scanner defectivity performance and pellicles support manufacturing requirements
EUV scanner defectivity performance and pellicles support manufacturing requirements DRAM, Logic non critical EUV layers: no Pellicle Critical layers: pellicle Reticle defectivity performance for 7nm logic node 110mm 144mm 2018 2019 Transmission EUV Defectivity level <5 adders / 10,000 wafers exposu
Slide 15: EUV – ASML Small Talk 2018
EUV – ASMLSMALLTALK2018 Veldhoven, November 8, 2018 • EUV Lithography … extend our Logic and DRAM customer roadmap • Our customers …. are preparing to ramp EUV at 7nm Logic, 16nm DRAM • EUV industrialization and infrastructure … is ready to support 2019 ramp • EUV roadmap … combines 0.33NA extension
Slide 16: Our EUV journey so far
Our EUV journey so far…. > 10 years to develop EUV technology with our customers 8 2006 2010 2013 2017 2018-19 ASML ships first full ASML ships first NA ASML ships first NA ASML ships first NA ASML NXE:3400B field EUV research 0.25 development 0.33 development 0.33 production installed base >25 syst
Slide 17: EUV technology extended for both 0.33NA and 0.55NA
EUV technology extended for both 0.33NA and 0.55NA Supporting applications beyond the next decade Public Slide 17 8 November 2018 EUV 0.33 platform will be extended to provide state of the art overlay and node to node productivity improvements EUV 0.33 NA 2016 2017 2018 2019 2020 2021 2022 2023 …202
Slide 18: In the same way 0.33NA enables 7nm Logic, 0.55NA EUV enables 3nm Logic
In the same way 0.33NA enables 7nm Logic, 0.55NA Public EUV enables 3nm Logic Slide 18 8 November 2018 Process simplification and improved device performance >> 50% cost reduction compared to multi-patterning schemes 3 to 6x cycle time reduction compared to multi-patterning for critical layers Best
Slide 19: Total patterning cost comparison: ArFi, EUV 0.33, EUV 0.55
In the same way 0.33NA enables 7nm Logic, 0.55NA Public EUV enables 3nm Logic Slide 19 8 November 2018 Total patterning cost comparison: ArFi, EUV 0.33, EUV 0.55 Process simplification and improved device performance Non Litho cost Litho cost >> 50% cost reduction compared to multi-patterning scheme
Slide 20: High NA system design completed, solid progress to support optics development
High NA system design completed, solid progress to Public support optics development and manufacturing Slide 20 8 November 2018 High NA optics metrology vessels Proto High NA mirror installed in cleanroom @ Zeiss SMT
Slide 21: Imec and ASML enter next stage of EUV collaboration
Imec and ASML enter next stage of EUV collaboration Collaboration will advance HVM and develop future lithography systems Public Slide 21 8 November 2018 2013 Advanced Patterning Center founded • First collaboration with pre-production EUV system NXE:3300 • Develop advanced CMOS integration, prepare
Slide 22: EUV – ASML Small Talk 2018
EUV – ASMLSMALLTALK2018 Veldhoven, November 8, 2018 Public Slide 22 8 November 2018 • EUV Lithography … extend our Logic and DRAM customer roadmap • Our customers …. are preparing to ramp EUV at 7nm Logic, 16nm DRAM • EUV industrialization and infrastructure … is ready to support 2019 ramp • EUV roa
Slide 23: Progress in EUV technology offering an aggressive productivity roadmap
Progress in EUV technology is offering an aggressive productivity roadmap enabled by better optical transmission Public Slide 23 8 November 2018 Reticle stage 250% 200% Illuminator Lens ity Collector 150% Productiv Wafer stage 100% More productivity at constant System power through better optical 50
Slide 24: EUV service follows a pay per wafer business model
EUV service follow a pay per/wafer pay business model and will benefit from productivity improvement Public Slide 24 8 November 2018 Reticle stage Illuminator stem Lens Collector Revenue/Sy Wafer stage More productivity at constant power through better optical Service transmission Productivity impro
Slide 25: Expect EUV value increase and cost reduction to bring EUV gross margin to DUV level
Expect EUV value increase and cost reduction to bring Public EUV gross margin to comparable level as DUV Slide 25 8 November 2018 Increased Customer Value Productivity improvement value (availability & wafer per day) Overlay and Imaging improvement System Process simplification & >40% ~ DUV improved
Slide 26: ASML EUV Lithography product and business opportunity Key Messages
ASML EUV Lithography product and business opportunity Key Messages Public Slide 26 8 November 2018 ASML EUV lithography extends our Logic and DRAM customers roadmap by providing lithography resolution improvement, state of the art overlay performance and year on year cost reduction Our customers are
Slide 27: Forward Looking Statements
Forward Looking Statements This document contains statements relating to certain projections, business trends and other matters that are forward-looking, including statements with respect to expected trends and outlook, strategy, bookings, expected financial results and trends, including expected sa
Slide 28: Investor Day ASML Small Talk 2018 Veldhoven
Public INVESTOR DAY ASML SMALL TALK 2018 VELDHOVEN