Asm International N.v. · EURONEXT:ASM

Asm International — Investor Day (July 2017)

42 slides from Asm International's investor day presentation, Jul 11, 2017

  1. Slide 1: Enabling Advanced Wafer Processing with New Materials

    ENABLING ADVANCED WAFER PROCESSING WITH NEW MATERIALS ASM International Analyst and Investor Technology Seminar Semicon West July 11, 2017

  2. Slide 2: Cautionary Note

    CAUTIONARY NOTE Cautionary Note Regarding Forward-Looking Statements: All matters discussed in this presentation, except for any historical data, are forward-looking statements. Forward- looking statements involve risks and uncertainties that could cause actual results to differ materially from thos

  3. Slide 3: Outline

    OUTLINE › New Materials and 3D: Moore’s law enablers • ASM technology focus: enabling new materials and new device integration roadmaps • Logic scaling › ALD • Key strengths of the technology • Selected applications in 3D-NAND, DRAM, logic and Emerging Memory › PECVD › Vertical Furnace › Epitaxy – I

  4. Slide 4: Outline

    OUTLINE › New Materials and 3D: Moore’s law enablers • ASM technology focus: enabling new materials and new device integration roadmaps • Logic scaling › ALD • Key strengths of the technology • Selected applications in 3D-NAND, DRAM, logic and Emerging Memory › PECVD › Vertical Furnace › Epitaxy – I

  5. Slide 5: Moore's Law Is Increasingly Enabled by New Materials and 3D Technologies

    MOORE’S LAW IS INCREASINGLY ENABLED BY NEW MATERIALS AND 3D TECHNOLOGIES 1990 1995 2000 2005 2010 2015 2020 2025 Scaling enabled by Litho Patterning Multi-Color ESL IEDM 2002 Spacers Self-aligned IEDM 2003 Scaling enabled by Materials IEDM 2007 High-mobility Low-k Materials Strained Si Scaling enabl

  6. Slide 6: Logic Scaling by Materials and 3D

    LOGIC SCALING BY MATERIALS AND 3D 2011 FinFET Device • Density scaling (continuing Moore’s law) driving towards higher mobility, lower resistivity and very conformal materials p- • Future systems will SiGe integrate much wider variety of materials and Next Device Architecture – device architectures

  7. Slide 7: Outline

    OUTLINE › New Materials and 3D: Moore’s law enablers • ASM technology focus: enabling new materials and new device integration roadmaps • Logic scaling › ALD • Key strengths of the technology • Selected applications in Logic, 3D-NAND, DRAM and Emerging Memory › PECVD › Vertical Furnace › Epitaxy – I

  8. Slide 8: ALD - Enabler of New Materials - Key Strengths of ALD

    ALD - ENABLER OF NEW MATERIALS - KEY STRENGTHS OF ALD Uniformity Step Coverage 438Հ SiO2 437.5Å 108Å TiN Scale Range 1.0Å 98% step coverage 0.14% Full range >438.5Å Interface Control Composition Control Excellent Atomically composition engineered control for interfaces to ternary alloys; optimize le

  9. Slide 9: Deploying the Advantages of ALD

    DEPLOYING THE ADVANTAGES OF ALD HAR (>10) Interface Composition Uniformity Low Step Coverage Control Control Temperature DRAM Capacitor     e-DRAM (FEOL)     High-k / Metal Gate Stack    e-DRAM (BEOL)      Double Patterning    Liners and Spacers     3D-NAND and Emerging Mem. 

  10. Slide 10: ASM Products: ALD

    ASM PRODUCTS ALD › Pulsar® XP  ALD Hf based high-k gate dielectrics  ALD metal oxides for etch stops, liners and pattern assist layers  Cross-flow reactor  Solid source delivery system Pulsar® XP › EmerALD® XP  ALD metal gate electrodes  ALD metal nitrides for capacitor electrodes  Showerhead

  11. Slide 11: FinFET Challenges: ALD Enables Further Scaling in 3D

    FINFET CHALLENGES: ALD ENABLES FURTHER SCALING IN 3D 22nm node 14nm node 10nm node Fin pitch [nm] 60 42 34 Gate pitch [nm] 90 70 54 Metal pitch [nm] 80 52 36 Source: Intel • Materials properties and channel length must be uniform over fin height • Conformal coverage required • Aspect ratios increase

  12. Slide 12: Extendibility of Hafnium Based Oxides

    EXTENDIBILITY OF HAFNIUM BASED OXIDES chipworks chipworks chipworks chipworks 45nm HK first RPMG 32 nm HK last RPMG 28nm HK first RPMG 22nm HK last RPMG Planar FET Planar FET Planar FET FinFET chipworks 10nm HK last RPMG 14nm HK last RPMG FinFET plus FinFET additional HK tuning layer | 12

  13. Slide 13: ASM Products: PEALD and PECVD

    ASM PRODUCTS PEALD AND PECVD › XP8-DCM  High productivity single wafer tool for both PEALD and PECVD applications  Accommodates up to 8 chambers by DCM  PEALD and PECVD can be integrated on the same platform DCM (Dual Chamber Module) | 13

  14. Slide 14: ALD for 3D-NAND Applications

    ALD FOR 3D-NAND APPLICATIONS BL (1) Source contact/Separation slit SiO Lateral WL Poly-Si or W Samsung VLSI Symp 2009 (1-1) High quality PEALD SiO for slit (1-2) High quality PEALD SiO for slit fill sidewall protection of source contact • High quality Low temperature & conformal SiO high quality SiO

  15. Slide 15: ALD for Spacer Defined Double/Quadruple Patterning

    ALD FOR SPACER DEFINED DOUBLE/QUADRUPLE PATTERNING Half pitch Pitch: P ALD SiO2 on resist 72nm Hard Mask Etch Pitch: 1/2 P 36nm In-situ trimming 2nd ALD Spacer PEALD SiO2 Spacer  Spacer Defined Double Patterning (SDDP) with ALD in production since 3xnm DRAM and 2xnm Flash  Spacer Defined Quadruple

  16. Slide 16: ALD for Spacer Defined Quadruple Patterning in DRAM

    ALD FOR SPACER DEFINED QUADRUPLE PATTERNING IN DRAM Half pitch Pitch: P Actual STI Mandrel 1st spacer Hard Mask Etch pattern 72nm Pitch: 1/2 P 36nm In-situ trimming 2nd ALD Spacer PEALD SiO2 Spacer TechInsights 2nd spacer Anisotropic Etch Pitch: 1/2 P Pitch: 1/4 P 18nm | 16

  17. Slide 17: Plasma Trimming and Smoothing Capability

    PLASMA TRIMMING AND SMOOTHING CAPABILITY Trimming • Uniformity of PEALD system used to trim and smoothen photoresist • Reshaping of photoresist upon exposure to Smoothing Ar/O2 plasma imec 2017 SPIE | 17

  18. Slide 18: ALD for Sub-20nm DRAM

    ALD FOR SUB-20NM DRAM 1. Bi-directional SDDP for hole patterning, introduced in D1x (LT-PEALD SiO) Storage Node • 2nd SDDP Contact BL W • PMD SiO after 1st SDDP BL 2 times SDDP Top view Cross sectional view (TechInsights) (TechInsights) 2. Sacrificial SiO (LT-PEALD SiO) TiN bottom electrode SiO sacr

  19. Slide 19: ALD Metal Hard Mask with Tunable Etch Selectivity

    ALD METAL HARD MASK WITH TUNABLE ETCH SELECTIVITY MOx has Dry etching resistance and it is wet strippable. MOx 3nm DRY etching WET etching 1.8 - 4.5 - 1.6 - 4.0 - Etch rate [a.u.] Etch rate [a.u.] 1.4 - 3.5 - 1.2 - 3.0 - 1.0 - 2.5 - 0.8 - 2.0 - 0.6 - 1.5 - 0.4 - 1.0 - 0.2 - 0.5 - 0.0 0.0 IBM 2017 SP

  20. Slide 20: Memory Hierarchy and Future Trends

    MEMORY HIERARCHY AND FUTURE TRENDS • DRAM and 3D-NAND scaling continues SRAM • Many opportunities for new STT materials and ALD processes in DRAM RAM Performance (speed) new memories FeRAM RRAM 3D Xpoint RRAM NAND New non-volatile memories Non-volatile memories Volatile memories Cost/bit | 20

  21. Slide 21: ALD Processes for 3D X-Point

    ALD PROCESSES FOR 3D X-POINT SDDP for WL and BL High Quality Low Temperature PEALD SiO2 gapfill Source:Micron High Quality PEALD SiO2 liner and gapfill Low Temperature PEALD SiO2 liner Source: TechInsights | 21

  22. Slide 22: Outline

    OUTLINE › New Materials and 3D: Moore’s law enablers • ASM technology focus: enabling new materials and new device integration roadmaps • Logic scaling › ALD • Key strengths of the technology • Selected applications in 3D-NAND, DRAM, logic and Emerging Memory › PECVD › Vertical Furnace › Epitaxy – I

  23. Slide 23: PECVD for 3D-NAND Applications

    PECVD FOR 3D-NAND APPLICATIONS (1) (1) PECVD TEOS applications BL Lateral WL TEOS • High throughput • Good wiw uniformity Samsung VLSI Symp 2009 • High quality • Stress control › New applications  Anti Reflective Layer: SiON  Amorphous Si  Amorphous Carbon Hard Mask | 23

  24. Slide 24: Outline

    OUTLINE › New Materials and 3D: Moore’s law enablers • ASM technology focus: enabling new materials and new device integration roadmaps • Logic scaling › ALD • Key strengths of the technology • Selected applications in 3D-NAND, DRAM, logic and Emerging Memory › PECVD › Vertical Furnace › Epitaxy – I

  25. Slide 25: ASM Products: Furnace CVD/Diffusion/Batch ALD

    ASM PRODUCTS FURNACE CVD /DIFFUSION /BATCH ALD › A412 PLUS  Dual boat/dual reactor system  Clustering of different applications between reactors possible – only vertical furnace in the market with this capability  Up to 150 product wafer load size › A400 for More than Moore Devices  Dual boat/du

  26. Slide 26: A400/A412 Furnace - Innovation

    A400/A412 FURNACE - INNOVATION Example 1: Novel Etch Stop Layer (ESL) Example 2: PolyImid Cure › Scaling of Logic devices requires conformal › PolyImid films are key components in Nanolayers with high etch resistivity Wafer Level Packaging. A highly uniform low temperature anneal process that cures

  27. Slide 27: Outline

    OUTLINE › New Materials and 3D: Moore’s law enablers • ASM technology focus: enabling new materials and new device integration roadmaps • Logic scaling › ALD • Key strengths of the technology • Selected applications in 3D-NAND, DRAM, logic and Emerging Memory › PECVD › Vertical Furnace › Epitaxy – I

  28. Slide 28: Epi Process Roadmap

    EPI PROCESS ROADMAP 7nm 5nm 3nm • Channel LOGIC N Type Undoped Si Undoped Si or HGAA HGAA P Type Undoped Si 30% SiGe or HGAA HGAA • Source Drain NSD 3% SiP 3-4% SiP >4% SiP (As?) PSD 40% SiGe >50% SiGe >50% SiGe (Ga?) 3D NAND 64 Stack 96 Stack 128 Stack • Memory Hole SEG SEG Poly Fill D1Y D1Z D1A DR

  29. Slide 29: Intrepid ES: Application Library

    INTREPID ES: APPLICATION LIBRARY Channel LOGIC • N-type • P-type • Si / SiGe HGAA SiGe / Si gate Si nanowire: Source Drain all around device 8nm radius • NSD Source: imec Source: imec • PSD 4-Fin resistance (Ω/µm) 3D NAND • Channel hole MEMORY Contact resistivity (Ω cm) DRAM Excellent uniformity, •

  30. Slide 30: Intrepid ES: Key Features

    INTREPID ES: KEY FEATURES • Low Chamber Volume • Dual Temperature Measurement: Pyrometer / TC • Isothermal Quartz Chamber: Closed Loop Control Intrepid ES delivers isothermal process modules for improved within wafer and wafer-to-wafer performance with the highest throughput | 30

  31. Slide 31: Advancements in Epitaxy: Low Temperature

    ADVANCEMENTS IN EPITAXY: LOW TEMPERATURE Conventional Epi Advanced Epi Quartz temp Quartz temp Hot wafer Cool wafer not controlled in control • Hot temperature processes: > 900°C • Low temperature processes: 400°C – 700°C • Pyrometer control for temperature is • Pyrometers are not accurate in this p

  32. Slide 32: Intrepid ES Key Features: Temperature Control

    INTREPID ES KEY FEATURES: TEMPERATURE CONTROL Wafer Pyrometer Quartz Pyrometer Graphite / wafer temperature Quartz temperature reading via pyrometer reading via pyrometer Blower speed adjusted to control quartz temperature Chamber Blower Temperature Control ASM’s “Inside Out” Approach Wafer Temperat

  33. Slide 33: Pyro Temperature: 200X Wafer Clean

    PYRO TEMPERATURE (°C): 200X WAFER CLEAN Wafer Pyrometer Temp. Wafer Pyrometer (°C) Temp (ºC) Quartz Pyrometer Temp. Quartz Pyrometer (°C) Temp (ºC) (C) Lot 1 Lot 2 Lot 3 Lot 4 Lot 5 Lot 6 Lot 7 Lot 8 Temp(°C) Lot 1 Lot 2 Lot 3 Lot 4 Lot 5 Lot 6 Lot 7 Lot 8 Pyro-Wafer Temp (°C) Pyro-QuartzTemp Pyro-Q

  34. Slide 34: Trends in Epitaxy: ASM Solutions

    TRENDS IN EPITAXY: ASM SOLUTIONS Epi Trends ASM Solutions Logic: GAA  stack layers with precise Small chamber volume interface control (Si / SiGe) TC control (pyrometry limitations <550°C) + isothermal kit Low temp. processing Higher GR achievable due to better precursor utilization and lower dilut

  35. Slide 35: Intrepid ES: Enhanced Stability

    INTREPID ES: ENHANCED STABILITY Intrepid with 1x Chamber Clean Intrepid ES with Multi-Wafer Clean 525 525 520 520 515 515 Film Thickness (Å) 510 Film Thickness (Å) 510 505 505 500 500 495 495 490 490 485 485 1%, 1σ wafer-to-wafer performance 0.3%, 1σ wafer-to-wafer performance 480 480 475 475 0 50 1

  36. Slide 36: Intrepid ES HVM Solution: Throughput

    INTREPID ES HVM SOLUTION: THROUGHPUT Throughput – per Chamber (a.u.) 6 10 Initial Intrepid Intrepid ES with Baseline Multi-Wafer Clean BACK Isothermal kit and multi-wafer clean deliver higher throughput for HVM | 36

  37. Slide 37: Previum: Integrated Surface Pre-Clean

    PREVIUM: INTEGRATED SURFACE PRE-CLEAN Previum Previum for C Removal H* Si0.44Ge0.56 oxide removal in Previum Radical (FTIR analysis) RPU RPU Optimized pre-clean process to remove SiGeOx  In-situ conversion /  In-situ conversion / sublimation for SiO2 AND SiGeOx sublimation for SiO2  H* radical fo

  38. Slide 38: Previum Performance

    PREVIUM PERFORMANCE Oxide Removal Particle Performance Monitor Wafer No. Adders 258 0 512 0 765 2 1018 0 1272 1 1526 2 1779 3 2033 0 2286 4 2539 4 2792 8 3046 1 Oxide Removal (Å) 43.3 Average adders: 2.1, >45nm WtW Removal Unif. (%) 1.1% Stable oxide removal demonstrated with low defectivity | 38

  39. Slide 39: Intrepid ES

    INTREPID ES › Delivers improved within-wafer and wafer-to-wafer performance with the highest throughputs › Qualified for production at a leading-edge foundry customer, targeting production applications in other industry segments › Integrated Previum pre-clean to address current and future surface pr

  40. Slide 40: Drive Innovation : Deliver Excellence

    DRIVE INNOVATION : DELIVER EXCELLENCE

  41. Slide 41: Intrepid ES Key Features: Chamber Design

    INTREPID ES KEY FEATURES: CHAMBER DESIGN Chamber Design Low chamber volume produces predictable laminar gas flow over the wafer Minimal chamber height over wafer Small Volume = Small Precursor Flows Low Gas Short Chamber Small Footprint BACK Consumption Cleans Abatement Reactor design enables high p

  42. Slide 42: Drive Innovation : Deliver Excellence

    DRIVE INNOVATION : DELIVER EXCELLENCE

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