Sanmina Corporation · NASDAQ:SANM
Sanmina — Oak-Mitsui Technologies — Technical Presentation
22 slides from Sanmina's technical presentation
Slide 1: FARADFLEX: The Next Generation of Buried Capacitance Material
EX omy ~~. STHENEXTGENERATIONOF = BURIED CAPACITANCE/MATERIAL FARADFLEX BC24-BC16-BC12-BC16T OAK-MITSUI TECHNOLOGIES 2
Slide 2: Introduction
INTRODUCTION •Background of Buried Capacitance •Performance Characteristics •PWB Manufacturing Process •Impedance Measurement •Noise Measurement •Conclusion
Slide 3: Current applications with Buried Capacitance
Current applications with Buried Capacitance Hi-end computers Network servers Network routers Demand for power distribution system with low impedance
Slide 4: Lower Impedance compared to discrete components
Lower Impedance compared to discrete components PWB with Buried Capacitance PWB with Discrete components
Slide 5: Demand for thin (<25micron) Buried Capacitance
Demand for thin (<25micron) Buried Capacitance Expectation by using Thin Capacitor Material - Improvement in electrical performance - Reduce cost - Reduce thickness of the board
Slide 6: Construction
Construction 16 micron 12 micron Polymer BC 12 Polymer BC 16T Dielectric with Hi-Dk Dielectric Filler 16 micron Polymer BC 16 Dielectric *Standard Copper thickness is 35micron **BC16T under development 24 micron Polymer BC 24 Dielectric
Slide 7: Electrical Properties
Electrical Properties Characteristics Condition Unit BC 24 BC 16 BC 12 BC 16T Capacitance 1GHz pF/in 900 1500 2000 10,000 Dk 1GHz N/A 4.6 4.6 4.6 25.0 Df 1GHz N/A 0.012 0.012 0.012 0.014 Dielectric Micron Nominal 24 16 12 16 Thickness Meter
Slide 8: Physical Properties
Physical Properties Characteristics Condition Unit BC 24 BC 16 BC 12 BC 16T Tg DMA Celsius 200 200 200 200 Peel Strength As received lb/in >6.0 >6.0 >6.0 >4.0 Young’s Modules JIS 2318 GPa 4.8 5.8 7.2 TBD Tensile JIS 2318 MPa 180 180 180 TBD Strength CTE IPC TM650 PPM 30 30 30 TBD Breakdown 1kV/sec V
Slide 9: PWB manufacturing process steps
1. Pre-Clean 2. Dry Film lamination 3. Expose Image 4. Pattern etching (Dual sides) 5. Black Oxide or Alternative B/O treated panel
Slide 10: Processing at major PCB facilities and results
• Substrates Processed at Major PCB Facilities • Standard I/L Processing • Results 1. No loss due to jams 2. No “blow out” of Clearance holes 3. No separation from border pattern 4. 100 % Yield at Hi-Pot (500 Volts) 5. Both Vertical Racked Black Oxide and Alternative Oxide used successfully
Slide 11: PWB Manufacturing Process
, ° FARADFLEX THE NEXT GENERATION OF BURIED CAPACITANCE” MATERIAL PWB Manufacturing Process PRESS- 0.000% 185CX2hr | ETCHING | BO | LAMINATE 0.000% ose © 0.005% 0, = 0.010% 0.010% 0.015% |- 0.020°% 0.015% = (>) — MMM THIN CAPACITIVE Y-AXIS 0.020% 0.025% = mm THIN CAPACITIVE X-AXIS ° 0.030% @ 50um CO
Slide 12: After processing drilling, desmear and plating
After processing drilling,desmear and plating
Slide 13: 4 Layer Board BC12
4 Layer Board FARADFLEX BC12 P.P P.P 0.6mm 0.6mm P.P 0.6mm P.P 0.6mm
Slide 14: 8 Layer Board BC12
a” FARADFLEX THE NEXT GENERATION OF BURIED CAPACITANCE™ MATERIAL PWB Examples 2 8 LAYER BOARD with MICRO-VIA 8 Layer Board L41 ce ee 2 if L FARADFLEX CORE i iF HE = HE i = a BS Bs oe i A E EE FEEEEEEEE ae Ags L5 - ee = gal Ten = ie - |S FARADFLEX CORE L8 } FARADFLEX BC12 OAK-MITSUI TECHNOLOGIES 2 U
Slide 15: 24 Layer Board BC12
24 Layer Board FARADFLEX BC12
Slide 16: Reliability test results
Micro-via Plating FARADFLEX BC24 Thermal Solder Shock FARADFLEX 288C x6 BC12 Reliability test Dielectric Withstanding Voltage : 500V Passed, No failure T-260 Time to Delamination : BC12 6.3min, BC24 5.2min Blind Via Plating Defects : No defects found Thermal Solder Shock – 6x : No defects fo
Slide 17: PWB Electrical Performance
Va FARADFLEX THE NEXT GENERATION OF BURIED CAPACITANCE” MATERIAL PWEB Electrical Perionnance MEASURE S., BY DIRECT STIMULUS INJECTION INTO THE COPPER PLANES VNA 4 LAYER TEST BOARD CROSS SECTION VIEW FILLER PREPREG DIELECTRIC LAYER UNDER TEST N FILLER PREPREG Le VIA HEIGHTS REMAIN CONSTANT FOR ALL DL
Slide 18: (Self Z) Significant Reduction on Impedance
(Self Z) Significant Reduction on Impedance
Slide 19: (Transfer Z) Significant Reduction on Impedance
(Transfer Z) Significant Reduction on Impedance
Slide 20: (Transfer Z) Significant Reduction of EMI
(Transfer Z) Significant Reduction of EMI SMA connector Vcc(3.3V) MPU MPU (40MHz) is mounted on the other side of the board. P.P 0.6mm P.P 0.6mm
Slide 21: Conclusion: The Product for High Speed Boards
• Thinner Materials for Buried CapacitanceTM are required for improved Impedance Performance at high frequency • Our New Substrate has excellent electrical performance and physical properties. • It is compatible with PCB processing; a truly “drop in” material. The Product for High Speed Boards FARAD
Slide 22: For more information contact
FARADFLEX TM For more information contact: John Andresakis VP of Strategic Technology (518) 686-8088 john.andresakis@oakmitsui.com or visit us at www.oakmitsui.com